Author: stepan Date: Fri Apr 9 15:33:59 2010 New Revision: 5393 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5393
Log: Drop the need for cpu_reset, it's really just a short cut to stage2. Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Added: trunk/src/arch/i386/lib/stages.c Modified: trunk/src/cpu/x86/car/cache_as_ram.lds trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Added: trunk/src/arch/i386/lib/stages.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/lib/stages.c Fri Apr 9 15:33:59 2010 (r5393) @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void skip_romstage(void) +{ + asm volatile ( + "/* set the boot_complete flag */\n" + "movl $0xffffffff, %%ebp\n" + "jmp __main\n" + ); +} + Modified: trunk/src/cpu/x86/car/cache_as_ram.lds ============================================================================== --- trunk/src/cpu/x86/car/cache_as_ram.lds Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/cpu/x86/car/cache_as_ram.lds Fri Apr 9 15:33:59 2010 (r5393) @@ -5,8 +5,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/dell/s1850/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -157,6 +157,8 @@ /* end IPMI garbage */ +#include "arch/i386/lib/stages.c" + static void main(unsigned long bist) { u8 b; @@ -277,7 +279,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/intel/jarrell/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -50,6 +50,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" #include "debug.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -75,7 +76,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -58,6 +58,7 @@ #include "northbridge/intel/i3100/raminit.c" #include "lib/generic_sdram.c" #include "../jarrell/debug.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -79,7 +80,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Set up the console */ Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/intel/truxton/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -58,6 +58,7 @@ #include "northbridge/intel/i3100/raminit_ep80579.c" #include "lib/generic_sdram.c" #include "../../intel/jarrell/debug.c" +#include "arch/i386/lib/stages.c" /* #define TRUXTON_DEBUG */ @@ -77,7 +78,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -51,6 +51,7 @@ #include "northbridge/intel/e7525/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -74,7 +75,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -52,6 +52,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -77,7 +78,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -52,6 +52,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -78,7 +79,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -53,6 +53,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -78,7 +79,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -53,6 +53,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -78,7 +79,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
