On 04/09/2010 07:56 PM, Rudolf Marek wrote:
>> That could be very helpful for me. This register (LDN 7 reg EF) seems to
>> be very interesting. Bit 0 is chip select, but also bits 2,4,5,6 are
>> used in bios code. Bit 6 probably is some watchdog setting - setting it
>> on with resetting other bits causes reboot in ~ a second.
>
> Hm the LDN 7 EF is not documented in old 0.4 version of datasheet.
>
>> Also there is some moment in bios code about test reg 2F @ LDN F4 - it
>> is toggled in some place and this could be important - may be enabling
>> some undocumented features.
>
> Yes no docs again,
Here is code fragment I mentioned - some bit is set then reset:
(Not sure now that this code runs at all)
seg003:E581 mov al, 7
seg003:E583 mov dx, 2Eh ; '.'
seg003:E586 out dx, al
seg003:E587 mov al, 0F4h ; '¯' ; LDN F4h ?
seg003:E589 inc dx
seg003:E58A out dx, al
seg003:E58B dec dx
seg003:E58C mov al, 2Fh ; '/'
seg003:E58E out dx, al
seg003:E58F mov al, 4
seg003:E591 inc dx
seg003:E592 out dx, al ; write 2F = 4
seg003:E593 dec dx
seg003:E594 mov cx, 0Ah
seg003:E597
seg003:E597 delay2: ; CODE XREF: seg003:E599j
seg003:E597 out 0EBh, al
seg003:E599 loop delay2
seg003:E59B mov al, 2Fh ; '/'
seg003:E59D out dx, al
seg003:E59E mov al, 0
seg003:E5A0 inc dx
seg003:E5A1 out dx, al ; write 2F = 0
seg003:E5A2 mov dx, 2Eh ; '.'
seg003:E5A5 mov al, 2 ; sio exit
seg003:E5A7 out dx, al
seg003:E5A8 out 0EBh, al
seg003:E5AA inc dx
seg003:E5AB mov al, 2
seg003:E5AD out dx, al
>
>>
>> Another interesting moment is checking for status of RI2 event (LDN 4
>> reg F1 bit 1) - it's almost first op in bios startup code. AFAICS RI2
>> event causes switch to chip 1 (Backup) and reboot - but there is no COM2
>> port on that board. And settings at reg 29 after boot told me that RI2
>> pin is switched to GPIO mode. So it is probably some debugging feature -
>> if we find the way to set RI2 event then it seems to be an easy way to
>> boot from backup bios.
>
> This bit is marked reserved.
Here is info from datasheet that I found. It is "Preliminary
Specification V0.3" for IT8718F:
LDN 04
APC/PME Status Register (PSR) (Index=F1h, Default=00h)
...
bit desc
4 0: No PS/2 Mouse Event Detected
1: PS/2 Mouse Event Detected
3 0: No Keyboard Event Detected
1: Keyboard Event Detected
2 0: No RI2# Event Detected
1: RI2# Event Detected
1 0: No RI1# Event Detected
1: RI1# Event Detected
0 0: No CIR event Detected
1: CIR event Detected
So it seems that bit 2 is RI2 Event. It's first what is tested in bios code.
Here is code fragment - it runs at very early startup - before
initializing CPU, HT etc:
seg003:447C loc_F447C: ; DATA XREF:
seg003:off_F447Ao
seg003:447C mov dx, 2Eh ; '.' ; enter SIO cfg mode
seg003:447F mov al, 87h ; 'Ç'
seg003:4481 out dx, al
seg003:4482 mov al, 1
seg003:4484 out dx, al
seg003:4485 mov al, 55h ; 'U'
seg003:4487 out dx, al
seg003:4488 mov al, 55h ; 'U'
seg003:448A out dx, al
seg003:448B mov cl, 4
seg003:448D mov dx, 2Eh ; '.'
seg003:4490 mov al, 7
seg003:4492 out dx, al
seg003:4493 out 0EBh, al
seg003:4495 inc dx
seg003:4496 mov al, cl
seg003:4498 out dx, al ; select LDN 4 - EC
seg003:4499 out 0EBh, al
seg003:449B mov cl, 0F1h ; '¸'
seg003:449D mov al, cl
seg003:449F mov dx, 2Eh ; '.'
seg003:44A2 out dx, al
seg003:44A3 out 0EBh, al
seg003:44A5 inc dx
seg003:44A6 in al, dx ; read F1 - APC/PME Status
seg003:44A7 out 0EBh, al
seg003:44A9 test al, 4 ; check bit 2 - RI2# Event
seg003:44AB jz short sio_exit_0
seg003:44AD mov cl, 7
seg003:44AF mov dx, 2Eh ; '.'
seg003:44B2 mov al, 7
seg003:44B4 out dx, al
seg003:44B5 out 0EBh, al
seg003:44B7 inc dx
seg003:44B8 mov al, cl
seg003:44BA out dx, al ; select LDN 7 - GPIO
seg003:44BB out 0EBh, al
seg003:44BD mov cl, 0EFh ; 'ÿ' ; reg EF
seg003:44BF mov al, cl
seg003:44C1 mov dx, 2Eh ; '.'
seg003:44C4 out dx, al
seg003:44C5 out 0EBh, al
seg003:44C7 inc dx
seg003:44C8 in al, dx ; read EF
seg003:44C9 out 0EBh, al
seg003:44CB test al, 1 ; test bit 0
seg003:44CD jnz short sio_exit_0
seg003:44CF mov cl, 0EFh ; 'ÿ'
seg003:44D1 mov al, cl
seg003:44D3 mov dx, 2Eh ; '.'
seg003:44D6 out dx, al
seg003:44D7 out 0EBh, al
seg003:44D9 inc dx
seg003:44DA in al, dx ; read EF
seg003:44DB out 0EBh, al
seg003:44DD or al, 1 ; set bit 0
seg003:44DF mov ah, al
seg003:44E1 mov dx, 2Eh ; '.'
seg003:44E4 mov al, cl
seg003:44E6 out dx, al ; write EF
seg003:44E7 out 0EBh, al
seg003:44E9 mov al, ah
seg003:44EB inc dx
seg003:44EC out dx, al
seg003:44ED out 0EBh, al
seg003:44EF mov al, 2
seg003:44F1 mov dx, 0CF9h ; reset
seg003:44F4 out dx, al
seg003:44F5 mov al, 6
seg003:44F7 out dx, al
>
>> BTW all info I have on this is from it8718 datasheet, but it seems that
>> the code is same for 8718 and 8720.
>>
>
> Hmm the LDN F4 is really some debug feature... Maybe someone should
> get new datasheet ;)
>
> Rudolf
>
>
--
Best regards,
Vadim Girlin
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