Author: stepan Date: Sun Apr 11 21:02:10 2010 New Revision: 5406 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5406
Log: The ADL855PC was never confirmed working (in fact it's pretty sure that code does not work as it is, but it's the only compile test case for i855pm). It's the only board left using an ICH4 that does not use CAR. Change that. Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/cpu/intel/socket_mPGA479M/Kconfig trunk/src/mainboard/digitallogic/adl855pc/Kconfig trunk/src/mainboard/digitallogic/adl855pc/romstage.c Modified: trunk/src/cpu/intel/socket_mPGA479M/Kconfig ============================================================================== --- trunk/src/cpu/intel/socket_mPGA479M/Kconfig Sun Apr 11 20:57:10 2010 (r5405) +++ trunk/src/cpu/intel/socket_mPGA479M/Kconfig Sun Apr 11 21:02:10 2010 (r5406) @@ -1,6 +1,7 @@ config CPU_INTEL_SOCKET_MPGA479M bool select CPU_INTEL_MODEL_69X + select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6DX select MMX select SSE Modified: trunk/src/mainboard/digitallogic/adl855pc/Kconfig ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/Kconfig Sun Apr 11 20:57:10 2010 (r5405) +++ trunk/src/mainboard/digitallogic/adl855pc/Kconfig Sun Apr 11 21:02:10 2010 (r5406) @@ -5,10 +5,12 @@ select NORTHBRIDGE_INTEL_I855 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_PIRQ_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select TINY_BOOTBLOCK config MAINBOARD_DIR string @@ -20,6 +22,16 @@ default "smartModule855" depends on BOARD_DIGITALLOGIC_ADL855PC +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_DIGITALLOGIC_ADL855PC + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_DIGITALLOGIC_ADL855PC + config IRQ_SLOT_COUNT int default 5 Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Apr 11 20:57:10 2010 (r5405) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Apr 11 21:02:10 2010 (r5406) @@ -57,7 +57,10 @@ #include "northbridge/intel/i855/reset_test.c" #include "lib/generic_sdram.c" -static void main(unsigned long bist) + +#include "cpu/intel/model_6bx/cache_as_ram_disable.c" + +void real_main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -67,7 +70,6 @@ }; if (bist == 0) { - early_mtrr_init(); #if 0 enable_lapic(); init_timer(); @@ -80,7 +82,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - #if 0 print_pci_devices(); @@ -89,50 +90,25 @@ if(!bios_reset_detected()) { enable_smbus(); #if 0 - dump_spd_registers(&memctrl[0]); - // dump_smbus_registers(); + dump_spd_registers(&memctrl[0]); + dump_smbus_registers(); #endif - memreset_setup(); sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } -#if 0 - else { - /* clear memory 1meg */ - __asm__ volatile( - "1: \n\t" - "movl %0, %%fs:(%1)\n\t" - "addl $4,%1\n\t" - "subl $4,%2\n\t" - "jnz 1b\n\t" - : - : "a" (0), "D" (0), "c" (1024*1024) - ); - - } -#endif #if 0 dump_pci_devices(); -#endif -#if 0 dump_pci_device(PCI_DEV(0, 0, 0)); -#endif -/* -#if 0 + // Check all of memory ram_check(0x00000000, msr.lo+(msr.hi<<32)); -#else -#if 0 // Check 16MB of memory @ 0 ram_check(0x00000000, 0x01000000); -#else // Check 16MB of memory @ 2GB ram_check(0x80000000, 0x81000000); #endif -#endif -*/ } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
