Author: stepan Date: Wed Apr 14 11:04:31 2010 New Revision: 5424 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5424
Log: fix digitallogic adl855pc compilation (and clean up the warnings while at it) Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/northbridge/intel/i855/debug.c trunk/src/northbridge/intel/i855/raminit.c trunk/src/northbridge/intel/i855/raminit.h Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Wed Apr 14 09:47:07 2010 (r5423) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Wed Apr 14 11:04:31 2010 (r5424) @@ -3,12 +3,10 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> -#if 0 -#include <arch/smp/lapic.h> -#endif #include <arch/hlt.h> //#include "option_table.h" #include <stdlib.h> +#include "pc80/udelay_io.c" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "console/console.c" @@ -16,13 +14,6 @@ #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" - -#if 0 -#include "cpu/p6/apic_timer.c" -#include "lib/delay.c" -#endif - -#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -30,24 +21,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - outb(0x0e, 0x0cf9); -} - -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -57,10 +30,7 @@ #include "northbridge/intel/i855/reset_test.c" #include "lib/generic_sdram.c" - -#include "cpu/intel/model_6bx/cache_as_ram_disable.c" - -void real_main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -93,7 +63,6 @@ dump_spd_registers(&memctrl[0]); dump_smbus_registers(); #endif - memreset_setup(); sdram_initialize(ARRAY_SIZE(memctrl), memctrl); Modified: trunk/src/northbridge/intel/i855/debug.c ============================================================================== --- trunk/src/northbridge/intel/i855/debug.c Wed Apr 14 09:47:07 2010 (r5423) +++ trunk/src/northbridge/intel/i855/debug.c Wed Apr 14 11:04:31 2010 (r5424) @@ -18,24 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * generic K8 debug code, used by mainboard specific romstage.c - * - */ -#if 1 -/* -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} -*/ - - static void print_debug_pci_dev(unsigned dev) { print_debug("PCI: "); @@ -46,7 +28,7 @@ print_debug_hex8((dev >> 12) & 0x07); } -static void print_pci_devices(void) +static inline void print_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -85,7 +67,7 @@ } } -static void dump_pci_devices(void) +static inline void dump_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -102,7 +84,7 @@ } } -static void dump_spd_registers(const struct mem_controller *ctrl) +static inline void dump_spd_registers(const struct mem_controller *ctrl) { int i; print_debug("\n"); @@ -134,37 +116,10 @@ } print_debug("\n"); } -#if 0 - device = ctrl->channel1[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\n"); - } -#endif } } -static void dump_smbus_registers(void) + +static inline void dump_smbus_registers(void) { int i; print_debug("\n"); @@ -194,4 +149,3 @@ print_debug("\n"); } } -#endif Modified: trunk/src/northbridge/intel/i855/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.c Wed Apr 14 09:47:07 2010 (r5423) +++ trunk/src/northbridge/intel/i855/raminit.c Wed Apr 14 11:04:31 2010 (r5424) @@ -19,6 +19,7 @@ */ #include <sdram_mode.h> +#include <delay.h> #define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1)) #define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5) @@ -85,20 +86,11 @@ pci_write_config32(ctrl->d0, 0xa0, dtc_reg); } -void udelay(int usecs) -{ - int i; - for(i = 0; i < usecs; i++) - outb(i & 0xff, 0x80); -} - #define delay() udelay(200) /* if ram still doesn't work do this function */ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) { - uint16_t word; - /* 0:0.0 */ /* pci_write_config32(PCI_DEV(0, 0, 0), 0x10, 0xe0000008); Modified: trunk/src/northbridge/intel/i855/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.h Wed Apr 14 09:47:07 2010 (r5423) +++ trunk/src/northbridge/intel/i855/raminit.h Wed Apr 14 11:04:31 2010 (r5424) @@ -28,5 +28,7 @@ uint16_t channel0[DIMM_SOCKETS]; }; +void sdram_initialize(int controllers, const struct mem_controller *ctrl); + #endif /* RAMINIT_H */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
