Index: src/mainboard/via/epia-en/Kconfig =================================================================== --- src/mainboard/via/epia-en/Kconfig (revision 5167) +++ src/mainboard/via/epia-en/Kconfig (working copy) @@ -1,40 +1,32 @@ -config BOARD_VIA_EPIA_CN - bool "EPIA-CN" +# Copied mostly from src/mainboard/via/epia-cn/Kconfig +# Jasper Aorangi, 2010, changes marked.(exept obv) +config BOARD_VIA_EPIA_EN + bool "EPIA-EN" select ARCH_X86 select CPU_VIA_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R - select SUPERIO_VIA_VT1211 - select ROMCC +#Select corect superio + select SUPERIO_WINBOND_W83697HF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR string - default via/epia-cn - depends on BOARD_VIA_EPIA_CN + default via/epia-en + depends on BOARD_VIA_EPIA_EN -#config DCACHE_RAM_BASE -# hex -# default 0xffef0000 -# depends on BOARD_VIA_EPIA_CN -# -#config DCACHE_RAM_SIZE -# hex -# default 0x8000 -# depends on BOARD_VIA_EPIA_CN - config MAINBOARD_PART_NUMBER string - default "EPIA-CN" - depends on BOARD_VIA_EPIA_CN + default "EPIA-EN" + depends on BOARD_VIA_EPIA_EN config RAMBASE hex default 0x4000 - depends on BOARD_VIA_EPIA_CN + depends on BOARD_VIA_EPIA_EN config IRQ_SLOT_COUNT int default 9 - depends on BOARD_VIA_EPIA_CN + depends on BOARD_VIA_EPIA_EN Index: src/mainboard/via/epia-en/devicetree.cb =================================================================== --- src/mainboard/via/epia-en/devicetree.cb (revision 5167) +++ src/mainboard/via/epia-en/devicetree.cb (working copy) @@ -1,3 +1,8 @@ +# Copied from src/maniboard/via/epia-cn/devicetree.cb +# with additions copied from src/mainboard/via/epia-n/devicetree.cb +# to account for differeing superio. +# Jasper Aorangi, 2010 + chip northbridge/via/cn700 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # AGP Bridge @@ -24,13 +29,14 @@ device pci 10.4 on end # EHCI device pci 10.5 on end # UDCI device pci 11.0 on # Southbridge LPC - chip superio/via/vt1211 # Super I/O +# Copied from epia-n, J.A + chip superio/winbond/w83697hf # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port + device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 @@ -39,15 +45,32 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # COM2 + device pnp 2e.3 off # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end + device pnp 2e.6 off # IR Port + io 0x60 = 0x000 + end + device pnp 2e.7 off # GPIO 1 + io 0x60 = 0x201 # 0x201 + end + device pnp 2e.8 off # GPIO 5 + io 0x60 = 0x330 # 0x330 + end + device pnp 2e.9 off # GPIO 2, 3,and 4 + io 0x60 = 0x000 # + end + device pnp 2e.a off # ACPI + io 0x60 = 0x000 # + end device pnp 2e.b on # HWM - io 0x60 = 0xec00 + io 0x60 = 0x290 + irq 0x70 = 0 end end end +# End copied section, J.A device pci 11.5 on end # AC'97 audio # device pci 11.6 off end # AC'97 Modem device pci 12.0 on end # Ethernet Index: src/mainboard/via/epia-en/romstage.c =================================================================== --- src/mainboard/via/epia-en/romstage.c (revision 5167) +++ src/mainboard/via/epia-en/romstage.c (working copy) @@ -17,11 +17,12 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Copied almost directly from src/mainboard/via/epia-n + * Changes marked. + * Jasper Aorangi, 2010 */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #include #include #include @@ -30,7 +31,7 @@ #include #include #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" @@ -39,8 +40,13 @@ #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" -#include "southbridge/via/vt8235/vt8235_early_serial.c" +// #include "southbridge/via/vt8235/vt8235_early_serial.c" +/* Add winbond stuff from epia-n, J.A*/ +#include "superio/winbond/w83697hf/w83697hf_early_serial.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) + + static void memreset_setup(void) { } @@ -89,15 +95,20 @@ .channel0 = { 0x50 }, }; -static void main(unsigned long bist) +/* Change this... why not J.A*/ +// static void main(unsigned long bist) +void main(unsigned long bist) { unsigned long x; device_t dev; /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - - enable_vt8235_serial(); + + /* Added next two lines from epia-n, J.A*/ + w83697hf_set_clksel_48(SERIAL_DEV); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); console_init(); Index: src/mainboard/via/epia-en/Makefile.inc =================================================================== --- src/mainboard/via/epia-en/Makefile.inc (revision 5167) +++ src/mainboard/via/epia-en/Makefile.inc (working copy) @@ -1,3 +1 @@ ROMCCFLAGS := -mcpu=c3 -O -include $(src)/mainboard/Makefile.romccboard.inc - Index: src/mainboard/via/epia-en/irq_tables.c =================================================================== --- src/mainboard/via/epia-en/irq_tables.c (revision 5167) +++ src/mainboard/via/epia-en/irq_tables.c (working copy) @@ -17,6 +17,10 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Jasper Aorangi, 2010 + * Copied directly from epia-cn with no modification for epia-en + * Must be wrong and will need updating. */ #include Index: src/mainboard/via/epia-en/mainboard.c =================================================================== --- src/mainboard/via/epia-en/mainboard.c (revision 5167) +++ src/mainboard/via/epia-en/mainboard.c (working copy) @@ -17,11 +17,15 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Jasper Aorangi 2010 + * copied almost entirely from src/mainboard/via/epia-cn/mainboard.c + * Modifications obviouse */ #include #include "chip.h" struct chip_operations mainboard_ops = { - CHIP_NAME("VIA EPIA-CN Mainboard") + CHIP_NAME("VIA EPIA-EN Mainboard") }; Index: src/mainboard/via/epia-en/romstage.c_from_epia-n_winbond =================================================================== --- src/mainboard/via/epia-en/romstage.c_from_epia-n_winbond (revision 0) +++ src/mainboard/via/epia-en/romstage.c_from_epia-n_winbond (revision 0) @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Copied almost directly from src/mainboard/via/epia-n/romstage.c + * Changes marked. I have left all the memory stuff the same as epia-cn so + * only real changes are the use of winbond for serial. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "console/console.c" +#include "lib/ramtest.c" +#include "northbridge/via/cn700/raminit.h" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "superio/winbond/w83697hf/w83697hf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) + +/* + * NOOB :: + * d0f0 - Device 0 Function 0 etc. + * Sure you say no commented code... Commented because I guess that + * epia-en is more like epia-cn in this regard + */ +// static const struct mem_controller ctrl = { +// .d0f0 = 0x0000, +// .d0f2 = 0x2000, +// .d0f3 = 0x3000, +// .d0f4 = 0x4000, +// .d0f7 = 0x7000, +// .d1f0 = 0x8000, +// .channel0 = { 0x50 }, +// }; + +static void memreset_setup(void) +{ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/via/cn700/raminit.c" + +static void enable_mainboard_devices(void) +{ + device_t dev; + u8 reg; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + if (dev == PCI_DEV_INVALID) + die("Southbridge not found!!!\n"); + + /* bit=0 means enable function (per VT8237R datasheet) + * 7 17.6 MC97 + * 6 17.5 AC97 + * 5 16.1 USB 2 + * 4 16.0 USB 1 + * 3 15.0 SATA and PATA + * 2 16.2 USB 3 + * 1 16.4 USB EHCI + */ + pci_write_config8(dev, 0x50, 0xC0); + + /*bit=0 means enable internal function (per VT8237R datasheet) + * 7 USB Device Mode + *bit=1 means enable internal function (per VT8237R datasheet) + * 6 Reserved + * 5 LAN Controller Clock Gating + * 4 LAN Controller + * 3 Internal RTC + * 2 Internal PS2 Mouse + * 1 Internal KBC Configuration + * 0 Internal Keyboard Controller + */ + pci_write_config8(dev, 0x51, 0x9d); +} + +/* Removed epia-n stuff here, and replaced with epia-cn stuff */ +static const struct mem_controller ctrl = { + .d0f0 = 0x0000, + .d0f2 = 0x2000, + .d0f3 = 0x3000, + .d0f4 = 0x4000, + .d0f7 = 0x7000, + .d1f0 = 0x8000, + .channel0 = { 0x50 }, +}; + +static void main(unsigned long bist) +{ + unsigned long x; + device_t dev; + + /* Enable multifunction for northbridge. */ + pci_write_config8(ctrl.d0f0, 0x4f, 0x01); + + w83697hf_set_clksel_48(SERIAL_DEV); + + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* From here on same as epia-cn */ + + uart_init(); + console_init(); + + print_spew("In romstage.c:main()\n"); + + enable_smbus(); + smbus_fixup(&ctrl); + + if (bist == 0) { + print_debug("doing early_mtrr\n"); + early_mtrr_init(); + } + + /* Halt if there was a built-in self test failure. */ + report_bist_failure(bist); + + print_debug("Enabling mainboard devices\n"); + enable_mainboard_devices(); + + ddr_ram_setup(&ctrl); + + /* ram_check(0, 640 * 1024); */ + + print_spew("Leaving romstage.c:main()\n"); + +} +