Author: stepan Date: Thu Apr 22 11:22:15 2010 New Revision: 5475 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5475
Log: fix compilation remaining geode boards Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/mainboard/amd/rumba/devicetree.cb trunk/src/mainboard/lippert/frontrunner/devicetree.cb trunk/src/northbridge/amd/gx2/chipsetinit.c trunk/src/northbridge/amd/gx2/grphinit.c trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/amd/gx2/northbridge.h trunk/src/northbridge/amd/gx2/northbridgeinit.c trunk/src/southbridge/amd/cs5536/chip.h trunk/src/southbridge/amd/cs5536/cs5536.c Modified: trunk/src/mainboard/amd/rumba/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/rumba/devicetree.cb Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/mainboard/amd/rumba/devicetree.cb Thu Apr 22 11:22:15 2010 (r5475) @@ -1,4 +1,6 @@ chip northbridge/amd/gx2 + register "setupflash" = "0" + #register "irqmap" = "0xaa5b" device apic_cluster 0 on chip cpu/amd/model_gx2 device apic 0 on end Modified: trunk/src/mainboard/lippert/frontrunner/devicetree.cb ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/devicetree.cb Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/mainboard/lippert/frontrunner/devicetree.cb Thu Apr 22 11:22:15 2010 (r5475) @@ -1,4 +1,6 @@ chip northbridge/amd/gx2 + register "setupflash" = "0" + #register "irqmap" = "0xaa5b" device pci_domain 0 on device pci 0.0 on end chip southbridge/amd/cs5535 Modified: trunk/src/northbridge/amd/gx2/chipsetinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/chipsetinit.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/chipsetinit.c Thu Apr 22 11:22:15 2010 (r5475) @@ -12,9 +12,8 @@ #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include "southbridge/amd/cs5536/cs5536.h" -extern int sizeram(void); /* the structs in this file only set msr.lo. But ... that may not always be true */ struct msrinit { @@ -22,13 +21,13 @@ msr_t msr; }; -/* Master Configuration Register for Bus Masters.*/ -struct msrinit SB_MASTER_CONF_TABLE[] = { - {USB1_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, /* NOTE: Must be 1st entry in table*/ - {USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, - {ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000}}, - {AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, - {MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000}}, +/* Master Configuration Register for Bus Masters. */ +static struct msrinit SB_MASTER_CONF_TABLE[] = { + { USB1_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, /* NOTE: Must be 1st entry in table */ + { USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, + { ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000} }, + { AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, + { MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000} }, /* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLIU_SB_GLD_MSR_CONF, 0x0*/ @@ -36,37 +35,38 @@ }; /* 5535_A3 Clock Gating*/ -struct msrinit CS5535_CLOCK_GATING_TABLE[] = { - { USB1_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { USB2_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - { GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - { MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, - { ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {0,{0,0}} +static struct msrinit CS5535_CLOCK_GATING_TABLE[] = { + { USB1_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { USB2_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, + { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, + { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} }, + { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { 0, {.hi=0, .lo=0x000000000} } }; /* 5536 Clock Gating*/ -struct msrinit CS5536_CLOCK_GATING_TABLE[] = { +static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { /* MSR Setting*/ - { GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - { GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - { MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/ - { ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {0,{0,0}} + { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, + { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, + { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} }, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */ + { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { 0, {.hi=0, .lo=0x000000000} } }; +#ifdef UNUSED_CODE struct acpiinit { unsigned short ioreg; unsigned long regdata; unsigned short iolen; }; -struct acpiinit acpi_init_table[] = { +static struct acpiinit acpi_init_table[] = { {ACPI_BASE+0x00, 0x01000000, 4}, {ACPI_BASE+0x08, 0, 4}, {ACPI_BASE+0x0C, 0, 4}, @@ -81,34 +81,28 @@ {PM_WKXD, 0x0000000A0, 4}, {0,0,0} }; +#endif /* return 1 if we are a 5536-based system */ -static int is_5536(void){ +static int is_5536(void) +{ msr_t msr; msr = rdmsr(GLIU_SB_GLD_MSR_CAP); msr.lo >>= 20; printk(BIOS_DEBUG, "is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf); return ((msr.lo&0xf) == 5); } -/* ***************************************************************************/ -/* **/ -/* * pmChipsetInit*/ -/* **/ -/* * Program ACPI LBAR and initialize ACPI registers.*/ -/* * */ -/* **/ -/* * Entry:*/ -/* * None*/ -/* **/ -/* * Exit:*/ -/* * None*/ -/* **/ -/* * Destroys:*/ -/* * None*/ -/* **/ -/* ***************************************************************************/ -static void -pmChipsetInit(void) { + +#ifdef UNUSED_CODE +/***************************************************************************** + * + * pmChipsetInit + * + * Program ACPI LBAR and initialize ACPI registers. + * + *****************************************************************************/ +static void pmChipsetInit(void) +{ unsigned long val = 0; unsigned short port; @@ -129,40 +123,43 @@ /* PM_SED*/ port = (PMLogic_BASE + 0x014); -/* mov eax, 0x057642 ; 100ms, works*/ val = 0x04601 ; /* 5ms*/ outl(val, port); /* PM_SIDD*/ port = (PMLogic_BASE + 0x020); -/* mov eax, 0x0AEC84 ; 200ms, works*/ val = 0x08C02 ; /* 10ms*/ outl(val, port); - /* GPIO24 OUT_AUX1 function is the external signal for 5535's vsb_working_aux*/ - /* which is de-asserted when 5535 enters Standby(S3 or S5) state.*/ - /* On Hawk, GPIO24 controls all voltage rails except Vmem and Vstandby. This means*/ - /* GX2 will be fully de-powered if this control de-asserts in S3/S5.*/ - /* */ - /* GPIO24 is setup in preChipsetInit for two reasons*/ - /* 1. GPIO24 at reset defaults to disabled, since this signal is vsb_work_aux on*/ - /* Hawk it controls the FET's for all voltage rails except Vstanby & Vmem.*/ - /* BIOS needs to enable GPIO24 as OUT_AUX1 & OUTPUT_EN early so it is driven*/ - /* by 5535.*/ - /* 2. Non-PM builds will require GPIO24 enabled for instant-off power button*/ - /* */ - - /* GPIO11 OUT_AUX1 function is the external signal for 5535's slp_clk_n which is asserted*/ - /* when 5535 enters Sleep(S1) state.*/ - /* On Hawk, GPIO11 is connected to control input of external clock generator*/ - /* for 14MHz, PCI, USB & LPC clocks.*/ - /* Programming of GPIO11 will be done by VSA PM code. During VSA Init. BIOS writes*/ - /* PM Core Virual Register indicating if S1 Clocks should be On or Off. This is based*/ - /* on a Setup item. We do not want to leave GPIO11 enabled because of a Hawk board*/ - /* problem. With GPIO11 enabled in S3, something is back-driving GPIO11 causing it to*/ - /* float to 1.6-1.7V.*/ - + /* GPIO24 OUT_AUX1 function is the external signal for 5535's + * vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or + * S5) state. On Hawk, GPIO24 controls all voltage rails except Vmem + * and Vstandby. This means GX2 will be fully de-powered if this + * control de-asserts in S3/S5. + */ + + /* GPIO24 is setup in preChipsetInit for two reasons + * 1. GPIO24 at reset defaults to disabled, since this signal is + * vsb_work_aux on Hawk it controls the FET's for all voltage + * rails except Vstanby & Vmem. BIOS needs to enable GPIO24 as + * OUT_AUX1 & OUTPUT_EN early so it is driven by 5535. + * 2. Non-PM builds will require GPIO24 enabled for instant-off power + * button + */ + + /* GPIO11 OUT_AUX1 function is the external signal for 5535's + * slp_clk_n which is asserted when 5535 enters Sleep(S1) state. + * On Hawk, GPIO11 is connected to control input of external clock + * generator for 14MHz, PCI, USB & LPC clocks. + * Programming of GPIO11 will be done by VSA PM code. During VSA + * Init. BIOS writes PM Core Virual Register indicating if S1 Clocks + * should be On or Off. This is based on a Setup item. We do not want + * to leave GPIO11 enabled because of a Hawk board problem. With + * GPIO11 enabled in S3, something is back-driving GPIO11 causing it + * to float to 1.6-1.7V. + */ } +#endif struct FLASH_DEVICE { unsigned char fType; /* Flash type: NOR or NAND */ @@ -170,7 +167,7 @@ unsigned long fMask; /* Flash size/mask */ }; -struct FLASH_DEVICE FlashInitTable[] = { +static struct FLASH_DEVICE FlashInitTable[] = { { FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */ { FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */ { FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */ @@ -179,12 +176,12 @@ #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) -uint32_t FlashPort[] = { +static uint32_t FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, MDD_LBAR_FLSH3 - }; +}; /*************************************************************************** * @@ -194,10 +191,6 @@ * correct size info. Call this routine only if flash needs to be * configured (don't call it if you want IDE). * - * Entry: - * Exit: - * Destroys: - * **************************************************************************/ static void ChipsetFlashSetup(void) { @@ -242,34 +235,34 @@ printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo); wrmsr(MDD_PIN_OPT, msr); } - printk(BIOS_DEBUG, "ChipsetFlashSetup--\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup--\n"); } -/* ***************************************************************************/ -/* **/ -/* * ChipsetGeodeLinkInit*/ -/* * Handle chipset specific GeodeLink settings here. */ -/* * Called from GeodeLink init code.*/ -/* **/ -/* * Entry:*/ -/* * Exit:*/ -/* * Destroys: GS*/ -/* **/ -/* ***************************************************************************/ +/**************************************************************************** + * + * ChipsetGeodeLinkInit + * + * Handle chipset specific GeodeLink settings here. + * Called from GeodeLink init code. + * + ****************************************************************************/ static void -ChipsetGeodeLinkInit(void){ +ChipsetGeodeLinkInit(void) +{ msr_t msr; unsigned long msrnum; unsigned long totalmem; if (is_5536()) return; + /* SWASIF for A1 DMA */ - /* Set all memory to "just above systop" PCI so DMA will work*/ - /* check A1*/ + /* Set all memory to "just above systop" PCI so DMA will work */ + + /* check A1 */ msrnum = MSR_SB_GLCP + 0x17; msr = rdmsr(msrnum); if ((msr.lo&0xff) == 0x11) @@ -280,13 +273,14 @@ totalmem = ~totalmem; totalmem &= 0xfffff; msr.lo = totalmem; - msr.hi = 0x20000000; /* Port 1 (PCI)*/ - msrnum = MSR_SB_GLIU + 0x20; /* */; + msr.hi = 0x20000000; /* Port 1 (PCI) */ + msrnum = MSR_SB_GLIU + 0x20; wrmsr(msrnum, msr); } void -chipsetinit (struct northbridge_amd_gx2_config *nb){ +gx2_chipsetinit (struct northbridge_amd_gx2_config *nb) +{ msr_t msr; struct msrinit *csi; int i; @@ -294,7 +288,10 @@ outb( P80_CHIPSET_INIT, 0x80); ChipsetGeodeLinkInit(); -#if 0 + + printk(BIOS_DEBUG, "Companion is a %s\n", is_5536()?"CS5536":"CS5535"); + +#ifdef UNUSED_CODE /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ { @@ -313,9 +310,8 @@ } #endif - if (!is_5536()) { - /* Setup USB. Need more details. #118.18*/ + /* Setup USB. Need more details. #118.18 */ msrnum = MSR_SB_USB1 + 8; msr.lo = 0x00012090; msr.hi = 0; @@ -328,24 +324,23 @@ outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE); outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT); - /* Allow IO read and writes during a ATA DMA operation.*/ - /* This could be done in the HD rom but do it here for easier debugging.*/ + /* Allow IO read and writes during a ATA DMA operation. */ + /* This could be done in the HD rom but do it here for easier debugging. */ msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100; wrmsr(msrnum, msr); - /* Enable Post Primary IDE.*/ + /* Enable Post Primary IDE. */ msrnum = GLPCI_SB_CTRL; msr = rdmsr(msrnum); msr.lo |= GLPCI_CRTL_PPIDE_SET; wrmsr(msrnum, msr); - - /* Set up Master Configuration Register*/ - /* If 5536, use same master config settings as 5535, except for OHCI MSRs*/ - if (is_5536()) + /* Set up Master Configuration Register */ + /* If 5536, use same master config settings as 5535, except for OHCI MSRs */ + if (is_5536()) i = 2; else i = 0; @@ -357,17 +352,15 @@ wrmsr(csi->msrnum, msr); // MSR - see table above } + /* Flash Setup */ + printk(BIOS_INFO, "%sDOING ChipsetFlashSetup()!\n", + nb->setupflash ? "" : "NOT "); - /* Flash Setup*/ - printk(BIOS_ERR, "%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT"); if (nb->setupflash) ChipsetFlashSetup(); + /* Set up Hardware Clock Gating */ - - /* */ - /* Set up Hardware Clock Gating*/ - /* */ /* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */ { if (is_5536()) @@ -381,5 +374,5 @@ wrmsr(csi->msrnum, msr); // MSR - see table above } } - } + Modified: trunk/src/northbridge/amd/gx2/grphinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/grphinit.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/grphinit.c Thu Apr 22 11:22:15 2010 (r5475) @@ -1,7 +1,11 @@ #include <arch/io.h> #include <stdint.h> #include <cpu/amd/vr.h> +#include <device/device.h> +#include "chip.h" +#include "northbridge.h" +// FIXME handle UMA properly. #define VIDEO_MB 8 // MB of video memory Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/northbridge.c Thu Apr 22 11:22:15 2010 (r5475) @@ -17,8 +17,6 @@ #include "../../../southbridge/amd/cs5536/cs5536.h" #define VIDEO_MB 8 -extern void graphics_init(void); - #define NORTHBRIDGE_FILE "northbridge.c" /* todo: add a resource record. We don't do this here because this may be called when @@ -190,7 +188,7 @@ } /* we have to do this here. We have not found a nicer way to do it */ -void +static void setup_gx2(void) { @@ -371,6 +369,7 @@ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } +#if 0 static void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; @@ -382,7 +381,6 @@ *best_p = best; } -#if 0 static u32 find_pci_tolm(struct bus *bus) { struct resource *min; @@ -396,6 +394,8 @@ return tolm; } #endif + +// FIXME handle UMA correctly. #define FRAMEBUFFERK 4096 static void pci_domain_set_resources(device_t dev) @@ -484,19 +484,17 @@ static void enable_dev(struct device *dev) { printk(BIOS_DEBUG, "gx2 north: enable_dev\n"); - void northbridgeinit(void); - void chipsetinit(struct northbridge_amd_gx2_config *nb); void do_vsmbios(void); + /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; - extern void cpubug(void); u32 tomk; printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n"); /* cpubug MUST be called before setup_gx2(), so we force the issue here */ northbridgeinit(); - cpubug(); - chipsetinit(nb); + cpubug(); + gx2_chipsetinit(nb); setup_gx2(); do_vsmbios(); graphics_init(); Modified: trunk/src/northbridge/amd/gx2/northbridge.h ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.h Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/northbridge.h Thu Apr 22 11:22:15 2010 (r5475) @@ -1,6 +1,15 @@ #ifndef NORTHBRIDGE_AMD_GX2_H #define NORTHBRIDGE_AMD_GX2_H -extern unsigned int gx2_scan_root_bus(device_t root, unsigned int max); +#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if defined(__PRE_RAM__) +#else +unsigned int gx2_scan_root_bus(device_t root, unsigned int max); +int sizeram(void); +void gx2_chipsetinit (struct northbridge_amd_gx2_config *nb); +void graphics_init(void); +void northbridgeinit(void); +#endif +#endif #endif /* NORTHBRIDGE_AMD_GX2_H */ Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Thu Apr 22 11:22:15 2010 (r5475) @@ -135,7 +135,6 @@ */ /* yes, this duplicates later code, but it seems that is how they want it done. */ -extern int sizeram(void); static void SysmemInit(struct gliutable *gl) { Modified: trunk/src/southbridge/amd/cs5536/chip.h ============================================================================== --- trunk/src/southbridge/amd/cs5536/chip.h Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/southbridge/amd/cs5536/chip.h Thu Apr 22 11:22:15 2010 (r5475) @@ -40,7 +40,6 @@ unsigned int com2_address; /* e.g. 0x2F8 */ unsigned int com2_irq; /* e.g. 3 */ unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */ - }; #endif /* _SOUTHBRIDGE_AMD_CS5536 */ Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Thu Apr 22 11:22:15 2010 (r5475) @@ -40,7 +40,7 @@ }; /* Master Configuration Register for Bus Masters.*/ -struct msrinit SB_MASTER_CONF_TABLE[] = { +static struct msrinit SB_MASTER_CONF_TABLE[] = { {USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, {ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}}, {AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, @@ -49,7 +49,7 @@ }; /* 5536 Clock Gating*/ -struct msrinit CS5536_CLOCK_GATING_TABLE[] = { +static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { /* MSR Setting*/ {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, @@ -65,7 +65,7 @@ u32 regdata; }; -struct acpiinit acpi_init_table[] = { +static struct acpiinit acpi_init_table[] = { {ACPI_IO_BASE + 0x00, 0x01000000}, {ACPI_IO_BASE + 0x08, 0}, {ACPI_IO_BASE + 0x0C, 0}, @@ -86,7 +86,7 @@ unsigned long fMask; /* Flash size/mask */ }; -struct FLASH_DEVICE FlashInitTable[] = { +static struct FLASH_DEVICE FlashInitTable[] = { {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */ {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */ {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */ @@ -95,7 +95,7 @@ #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) -u32 FlashPort[] = { +static u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, @@ -512,12 +512,16 @@ } } -/* ***************************************************************************/ -/* **/ -/* * ChipsetInit */ -/* Called from northbridge init (Pre-VSA). */ -/* **/ -/* ***************************************************************************/ +/**************************************************************************** + * + * ChipsetInit + * + * Called from northbridge init (Pre-VSA). + * + * NOTE! This function is NOT called if the CS5536 is combined with + * an AMD Geode GX2. It's ONLY used on Geode LX based systems. + * + ****************************************************************************/ void chipsetinit(void) { device_t dev; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
