Author: myles Date: Fri Apr 30 19:11:03 2010 New Revision: 5512 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5512
Log: Get rid of a few more warnings. Signed-off-by: Myles Watson <[email protected]> Acked-by: Myles Watson <[email protected]> Modified: trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/northbridge/amd/amdfam10/Makefile.inc trunk/src/northbridge/amd/amdfam10/debug.c trunk/src/northbridge/amd/amdfam10/get_pci1234.c trunk/src/northbridge/amd/amdfam10/northbridge.h trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/amd/amdmct/mct/mct_d.c trunk/src/northbridge/intel/i3100/raminit.c trunk/src/northbridge/via/vx800/vga.c trunk/src/southbridge/intel/esb6300/esb6300_smbus.h trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/mainboard/arima/hdama/romstage.c Fri Apr 30 19:11:03 2010 (r5512) @@ -1,10 +1,10 @@ #include <stdint.h> +#include <string.h> #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> -#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Fri Apr 30 19:11:03 2010 (r5512) @@ -36,7 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX1.C has no SMBus; the setup is hard-wired. */ -void cs5536_enable_smbus(void) +static void cs5536_enable_smbus(void) { } Modified: trunk/src/northbridge/amd/amdfam10/Makefile.inc ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Makefile.inc Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdfam10/Makefile.inc Fri Apr 30 19:11:03 2010 (r5512) @@ -10,4 +10,3 @@ obj-$(CONFIG_GENERATE_ACPI_TABLES) += sspr5.o obj-y += get_pci1234.o - Modified: trunk/src/northbridge/amd/amdfam10/debug.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/debug.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdfam10/debug.c Fri Apr 30 19:11:03 2010 (r5512) @@ -26,7 +26,7 @@ static inline void print_debug_addr(const char *str, void *val) { -#if CACHE_AS_RAM_ADDRESS_DEBUG == 1 +#if defined(CACHE_AS_RAM_ADDRESS_DEBUG) && CACHE_AS_RAM_ADDRESS_DEBUG == 1 printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); #endif } Modified: trunk/src/northbridge/amd/amdfam10/get_pci1234.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/get_pci1234.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdfam10/get_pci1234.c Fri Apr 30 19:11:03 2010 (r5512) @@ -55,6 +55,7 @@ * */ +#include "northbridge.h" void get_pci1234(void) { Modified: trunk/src/northbridge/amd/amdfam10/northbridge.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.h Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdfam10/northbridge.h Fri Apr 30 19:11:03 2010 (r5512) @@ -21,5 +21,6 @@ #define NORTHBRIDGE_AMD_AMDFAM10_H u32 amdfam10_scan_root_bus(device_t root, u32 max); +void get_pci1234(void); #endif /* NORTHBRIDGE_AMD_AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Fri Apr 30 19:11:03 2010 (r5512) @@ -2511,9 +2511,8 @@ unsigned SlowAccessMode = 0; #endif - long dimm_mask = meminfo->dimm_mask & 0x0f; - #if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ + long dimm_mask = meminfo->dimm_mask & 0x0f; /* for REG DIMM */ dword = 0x00111222; dwordx = 0x002f0000; @@ -2578,6 +2577,7 @@ #endif #if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ + long dimm_mask = meminfo->dimm_mask & 0x0f; /* for UNBUF DIMM */ dword = 0x00111222; dwordx = 0x002f2f00; Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Fri Apr 30 19:11:03 2010 (r5512) @@ -528,7 +528,7 @@ unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128; #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 - unsigned cpu_f0_f1; + unsigned cpu_f0_f1 = 0; #endif if(Pass == DQS_FIRST_PASS) { Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Fri Apr 30 19:11:03 2010 (r5512) @@ -42,8 +42,6 @@ struct DCTStatStruc *pDCTstatA); static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, @@ -478,6 +476,8 @@ #ifdef UNUSED_CODE static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA); +static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* Clear MC4_STS for all Nodes in the system. This is required in some Modified: trunk/src/northbridge/intel/i3100/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/intel/i3100/raminit.c Fri Apr 30 19:11:03 2010 (r5512) @@ -944,7 +944,7 @@ u32 drc; u32 data32; u32 mode_reg; - u32 *iptr; + u32 const *iptr; u16 data16; static const struct { u32 clkgr[4]; Modified: trunk/src/northbridge/via/vx800/vga.c ============================================================================== --- trunk/src/northbridge/via/vx800/vga.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/via/vx800/vga.c Fri Apr 30 19:11:03 2010 (r5512) @@ -126,6 +126,7 @@ return res; } +#ifdef UNUSED_CODE void write_protect_vgabios(void) { device_t dev; @@ -141,6 +142,7 @@ //if(dev) // pci_write_config8(dev, 0x61, 0xff); */ } +#endif extern u8 acpi_sleep_type; static void vga_init(device_t dev) Modified: trunk/src/southbridge/intel/esb6300/esb6300_smbus.h ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_smbus.h Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/southbridge/intel/esb6300/esb6300_smbus.h Fri Apr 30 19:11:03 2010 (r5512) @@ -14,6 +14,8 @@ #define SMBUS_TIMEOUT (100*1000*10) +#include <delay.h> + static int smbus_wait_until_ready(unsigned smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Fri Apr 30 19:11:03 2010 (r5512) @@ -19,9 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val); #ifdef UNUSED_CODE +int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val); + static int set_ht_link_mcp55(uint8_t ht_c_num) { unsigned vendorid = 0x10de; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
