Hi all, this is a RFC. While Joseph, Idwer and myself convened on IRC for the past two days trying to get CAR working on the P6 family of CPUs, we found that -
The Intel CAR code works as is on Tualatin cores, L2 cache fully enabled The same code works for me on a Katmai, but only L1 cache is enabled This code does not boot at all for Idwer who also has a Katmai, and has stumped everyone We need to port a piece of long code from coreboot v1 that initializes the off-chip L2 cache found on Klamath/Deschutes/Katmai CPUs. They are respectively models 63x,65x and 67x. 16k of L1 is enough. We're only using 4k for CAR on Intel. It was written in C. I looked at the OEM BIOS for P2B-LS and L2 is initialized from the "inner BIOS", like the RAM stage of coreboot, when RAM is fully up and running. This means this can go into model_6xx_init(), which is prefereable as I just need to make enough adjustments to make it work again. Joseph OTOH suggests that I should port this code into cache_as_ram.inc which is much earlier, actually before motherboard romstage. This code is assembly, meaning I'll need to port this thing back to assembly. Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc? A patch to separate model 67x from model 6xx will soon come, either from me or Joseph. A similar one could be done for 65x and 63x. I do not have 66x Celerons to test so I cannot ascertain if this special attention will be needed for them. Thanks Keith -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
