Author: oxygene Date: Sun May 9 23:15:13 2010 New Revision: 5539 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5539
Log: Move includes to where they are needed. This allows to simplify romstage.c files in mainboards. Signed-off-by: Patrick Georgi <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/arch/i386/include/stddef.h trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/include/cpu/amd/model_10xxx_msr.h trunk/src/northbridge/amd/amdht/ht_wrapper.c trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Modified: trunk/src/arch/i386/include/stddef.h ============================================================================== --- trunk/src/arch/i386/include/stddef.h Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/arch/i386/include/stddef.h Sun May 9 23:15:13 2010 (r5539) @@ -8,7 +8,9 @@ typedef int wchar_t; typedef unsigned int wint_t; +#ifndef NULL #define NULL ((void *)0) +#endif #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Sun May 9 23:15:13 2010 (r5539) @@ -1,6 +1,7 @@ /* 2005.6 by yhlu * 2006.3 yhlu add copy data from CAR to ram */ +#include <string.h> #include <arch/stages.h> #include "cpu/amd/car/disable_cache_as_ram.c" Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun May 9 23:15:13 2010 (r5539) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <northbridge/amd/amdmct/amddefs.h> +#include <cpu/amd/mtrr.h> /* * Default MSR and errata settings. Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Sun May 9 23:15:13 2010 (r5539) @@ -18,6 +18,12 @@ */ #include "defaults.h" +#include <stdlib.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <northbridge/amd/amdht/AsPsDefs.h> +#include <northbridge/amd/amdht/porting.h> //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef SET_FIDVID Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/quadcore/quadcore.c Sun May 9 23:15:13 2010 (r5539) @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> #ifndef SET_NB_CFG_54 #define SET_NB_CFG_54 1 Modified: trunk/src/include/cpu/amd/model_10xxx_msr.h ============================================================================== --- trunk/src/include/cpu/amd/model_10xxx_msr.h Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/include/cpu/amd/model_10xxx_msr.h Sun May 9 23:15:13 2010 (r5539) @@ -20,6 +20,8 @@ #ifndef CPU_AMD_MODEL_10XXX_MSR_H #define CPU_AMD_MODEL_10XXX_MSR_H +#include <cpu/x86/msr.h> + #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f #define LS_CFG_MSR 0xC0011020 Modified: trunk/src/northbridge/amd/amdht/ht_wrapper.c ============================================================================== --- trunk/src/northbridge/amd/amdht/ht_wrapper.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/northbridge/amd/amdht/ht_wrapper.c Sun May 9 23:15:13 2010 (r5539) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <northbridge/amd/amdfam10/amdfam10.h> /*---------------------------------------------------------------------------- * TYPEDEFS, DEFINITIONS AND MACROS Modified: trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c Sun May 9 23:15:13 2010 (r5539) @@ -19,6 +19,7 @@ #include "mct_d.h" +#include <cpu/amd/mtrr.h> static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr); static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType); Modified: trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c ============================================================================== --- trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Sun May 9 23:15:13 2010 (r5539) @@ -19,6 +19,7 @@ */ #include <arch/romcc_io.h> +#include <device/pnp_def.h> /* All known/supported SMSC Super I/Os have the same logical device IDs * for the serial ports (COM1, COM2). -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
