Just fund a Celeron coppermine (686), The chipset of the mainboard seams to be mostly supported so shouldn't take to long to port and test. L2 is 128kb.
Mvh Anders ----- Reply message ----- Fra: "Keith Hui" <[email protected]> Dato: fre., maj 14, 2010 05:30 Emne: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this Til: "Joseph Smith" <[email protected]> Cc: <[email protected]> On Thu, May 13, 2010 at 10:28 PM, Joseph Smith <[email protected]> wrote: > On 05/13/2010 10:03 PM, Keith Hui wrote: >> >> Hi all, >> >> This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other >> related changes (below), so it is gzipped. I may have committed a few >> "crimes" here, but anyway... >> >> First, I found out why the debug output isn't correct - A typo caused >> the cache size to got lost amid the shuffle. It has been fixed in this >> version. >> >> This patch: >> 1. Brings back L2 initialization from coreboot v1 for family 63x,65x >> and 67x CPUs. Need someone with a Mendocino Celeron to see if the >> entire 128k of L2 is still enabled. >> 2. Split model_67x/65x and model_63x from model_6xx. model_67x also >> serves model 65x because they share too much code. Also included are >> Intel microcode for all CPUs in these families. There's just one file >> for all microcodes in one family. >> 3. In Slot 1 Makefile.inc, conditionally bring in sources in models >> 63x/67x/6bx only when the proper config has been selected in Kconfig. >> Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has >> been selected. >> 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the >> mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above. >> 5. Blocked out some apparently unused #includes from model_6xx_init.c. >> Once we're sure nothing really are using it, then remove them. >> >> Bootlog with a PIII 600MHz can be found here: >> http://coreboot.pastebin.com/PNUzJXZT >> >> Have fun, bon appetit and cheers. >> >> Signed-off-by: Keith Hui<[email protected]> > > This looks awesome Keith! Great Work :-) > I can only see one thing that needs fixing and it is cosmetic: > > Lines 394-395 of bootlog look good: > > CPU: vendor Intel device 673 > CPU: family 06, model 07, stepping 03 > > > But, Line 411 of bootlog: CPU: . > > + /* Print processor name */ > + fill_processor_name(processor_name); > + printk(BIOS_INFO, "CPU: %s.\n", processor_name); > > Is the %s not working? > I think that's because Katmai doesn't support processor brand string through CPUID. See page 3-197, volume 2A, Intel Software Developer's Manual It's cosmetic. This code can be removed from model 63x and 67x in the next patch. Thanks Keith -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
