Author: ruik Date: Mon May 17 00:26:25 2010 New Revision: 5563 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5563
Log: Sorry for this. I fixed that reverting the change for ROMCC. Signed-off-by: Rudolf Marek <[email protected]> Acked-by: Rudolf Marek <[email protected]> Modified: trunk/src/include/cpu/x86/cache.h Modified: trunk/src/include/cpu/x86/cache.h ============================================================================== --- trunk/src/include/cpu/x86/cache.h Sun May 16 23:51:34 2010 (r5562) +++ trunk/src/include/cpu/x86/cache.h Mon May 17 00:26:25 2010 (r5563) @@ -23,6 +23,17 @@ /* the memory clobber prevents the GCC from reordering the read/write order of CR0 */ + */ + +#if defined(__GNUC__) + +/* +Need this because ROMCC fails here with: + +cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: +0x1559920 asm Internal compiler error: lhs 1 regcm == 0 +*/ + static inline unsigned long read_cr0(void) { unsigned long cr0; @@ -35,6 +46,23 @@ asm volatile ("movl %0, %%cr0" : : "r" (cr0) : "memory"); } +#else + +static inline unsigned long read_cr0(void) +{ + unsigned long cr0; + asm volatile ("movl %%cr0, %0" : "=r" (cr0)); + return cr0; +} + +static inline void write_cr0(unsigned long cr0) +{ + asm volatile ("movl %0, %%cr0" : : "r" (cr0)); +} + +#endif + + static inline void invd(void) { asm volatile("invd" ::: "memory"); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
