Author: ruik Date: Mon May 17 00:32:58 2010 New Revision: 5564 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5564
Log: Sorry for this for second time. Now compile tested for both cases ;) Signed-off-by: Rudolf Marek <[email protected]> Acked-by: Rudolf Marek <[email protected]> Modified: trunk/src/include/cpu/x86/cache.h Modified: trunk/src/include/cpu/x86/cache.h ============================================================================== --- trunk/src/include/cpu/x86/cache.h Mon May 17 00:26:25 2010 (r5563) +++ trunk/src/include/cpu/x86/cache.h Mon May 17 00:32:58 2010 (r5564) @@ -23,8 +23,6 @@ /* the memory clobber prevents the GCC from reordering the read/write order of CR0 */ - */ - #if defined(__GNUC__) /* @@ -46,6 +44,11 @@ asm volatile ("movl %0, %%cr0" : : "r" (cr0) : "memory"); } +static inline void wbinvd(void) +{ + asm volatile ("wbinvd" ::: "memory"); +} + #else static inline unsigned long read_cr0(void) @@ -60,19 +63,18 @@ asm volatile ("movl %0, %%cr0" : : "r" (cr0)); } -#endif +static inline void wbinvd(void) +{ + asm volatile ("wbinvd"); +} +#endif static inline void invd(void) { asm volatile("invd" ::: "memory"); } -static inline void wbinvd(void) -{ - asm volatile ("wbinvd" ::: "memory"); -} - static inline void enable_cache(void) { unsigned long cr0; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
