On Sat, Jun 5, 2010 at 3:11 PM, Peter Stuge <[email protected]> wrote: > I have several issues with this commit. I pointed out at least one of > them already very long ago!
The attached patch addresses some of the issues. It mostly moves drivers to southbridge/ti/ and southbridge/dec/ Signed-off-by: Myles Watson <[email protected]> >> +++ trunk/src/include/device/pci_ids.h Fri Jun 4 21:53:55 2010 >> (r5609) >> @@ -696,6 +696,7 @@ >> #define PCI_DEVICE_ID_TI_4410 0xac41 >> #define PCI_DEVICE_ID_TI_4451 0xac42 >> #define PCI_DEVICE_ID_TI_1420 0xac51 >> +#define PCI_DEVICE_ID_TI_1520 0xAC55 > > Somewhat minor, but please use lower case for a-f to look like other > values in the file. Unfortunately, this is not consistent in that file, but I changed it so at least it's consistent within TI values. > >> @@ -1741,6 +1742,10 @@ >> #define PCI_DEVICE_ID_CCD_B00C 0xb00c >> #define PCI_DEVICE_ID_CCD_B100 0xb100 >> >> +#define PCI_VENDOR_ID_NOKIA 0x13B8 // Nokia Telecommunications oy >> +#define PCI_VENDOR_ID_NOKIA_WIRELESS 0x1603 // Nokia Wireless >> Communications >> +#define PCI_VENDOR_ID_NOKIA_HOME 0x1622 // Nokia Home Communications Removed. Thanks, Myles
Index: src/southbridge/Kconfig =================================================================== --- src/southbridge/Kconfig (revision 5619) +++ src/southbridge/Kconfig (working copy) @@ -1,5 +1,6 @@ source src/southbridge/amd/Kconfig source src/southbridge/broadcom/Kconfig +source src/southbridge/dec/Kconfig source src/southbridge/intel/Kconfig source src/southbridge/nvidia/Kconfig source src/southbridge/ricoh/Kconfig Index: src/southbridge/Makefile.inc =================================================================== --- src/southbridge/Makefile.inc (revision 5619) +++ src/southbridge/Makefile.inc (working copy) @@ -1,5 +1,6 @@ subdirs-y += amd subdirs-y += broadcom +subdirs-y += dec subdirs-y += intel subdirs-y += nvidia subdirs-y += ricoh Index: src/southbridge/dec/Kconfig =================================================================== --- src/southbridge/dec/Kconfig (revision 0) +++ src/southbridge/dec/Kconfig (revision 0) @@ -0,0 +1 @@ +source src/southbridge/dec/21143/Kconfig Index: src/southbridge/dec/Makefile.inc =================================================================== --- src/southbridge/dec/Makefile.inc (revision 0) +++ src/southbridge/dec/Makefile.inc (revision 0) @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOUTHBRIDGE_DEC_21143) += 21143 Property changes on: src/southbridge/dec/21143 ___________________________________________________________________ Added: svn:mergeinfo Index: src/southbridge/dec/21143/21143pd.c =================================================================== --- src/southbridge/dec/21143/21143pd.c (revision 5619) +++ src/southbridge/dec/21143/21143pd.c (working copy) @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Bertens <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <console/console.h> - -/** - * The following should be set in the mainboard-specific Kconfig file. - */ -#if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \ - !defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \ - !defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION)) -#error "you must supply these values in your mainboard-specific Kconfig file" -#endif - -/* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */ -/* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */ -/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */ - -/** - * This driver take the values from Kconfig and load them in the registers - */ -static void dec_21143pd_enable( device_t dev ) -{ - printk( BIOS_DEBUG, "Init of DECchip 21143PD/TD Kconfig style\n"); - // Command and Status Configuration Register (Offset 0x04) - pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION ); - printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) ); - // Cache Line Size Register (Offset 0x0C) - pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE ); - printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) ); - // Expansion ROM Base Address Register (Offset 0x30) - pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS ); - printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) ); - return; -} - -static struct device_operations dec_21143pd_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = dec_21143pd_enable, - .scan_bus = 0, -}; - -static const struct pci_driver dec_21143pd_driver __pci_driver = { - .ops = &dec_21143pd_ops, - .vendor = PCI_VENDOR_ID_DEC, - .device = PCI_DEVICE_ID_DEC_21142, -}; Index: src/southbridge/dec/21143/Kconfig =================================================================== --- src/southbridge/dec/21143/Kconfig (revision 0) +++ src/southbridge/dec/21143/Kconfig (revision 0) @@ -0,0 +1,2 @@ +config SOUTHBRIDGE_DEC_21143 + bool Index: src/southbridge/dec/21143/Makefile.inc =================================================================== --- src/southbridge/dec/21143/Makefile.inc (revision 5619) +++ src/southbridge/dec/21143/Makefile.inc (working copy) @@ -1,2 +1,2 @@ -driver-$(CONFIG_DRIVERS_DEC_21143PD) += 21143pd.o +driver-y += 21143.o Index: src/southbridge/dec/21143/21143.c =================================================================== --- src/southbridge/dec/21143/21143.c (revision 5619) +++ src/southbridge/dec/21143/21143.c (working copy) @@ -40,9 +40,9 @@ /** * This driver take the values from Kconfig and load them in the registers */ -static void dec_21143pd_enable( device_t dev ) +static void dec_21143_enable( device_t dev ) { - printk( BIOS_DEBUG, "Init of DECchip 21143PD/TD Kconfig style\n"); + printk( BIOS_DEBUG, "Init of DECchip 21143 Kconfig style\n"); // Command and Status Configuration Register (Offset 0x04) pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION ); printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) ); @@ -55,16 +55,16 @@ return; } -static struct device_operations dec_21143pd_ops = { +static struct device_operations dec_21143_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = dec_21143pd_enable, + .init = dec_21143_enable, .scan_bus = 0, }; -static const struct pci_driver dec_21143pd_driver __pci_driver = { - .ops = &dec_21143pd_ops, +static const struct pci_driver dec_21143_driver __pci_driver = { + .ops = &dec_21143_ops, .vendor = PCI_VENDOR_ID_DEC, .device = PCI_DEVICE_ID_DEC_21142, }; Property changes on: src/southbridge/dec/21143/21143.c ___________________________________________________________________ Added: svn:mergeinfo Index: src/southbridge/ti/Kconfig =================================================================== --- src/southbridge/ti/Kconfig (revision 5619) +++ src/southbridge/ti/Kconfig (working copy) @@ -19,3 +19,4 @@ source src/southbridge/ti/pci7420/Kconfig source src/southbridge/ti/pcixx12/Kconfig +source src/southbridge/ti/pci1x2x/Kconfig Index: src/southbridge/ti/Makefile.inc =================================================================== --- src/southbridge/ti/Makefile.inc (revision 5619) +++ src/southbridge/ti/Makefile.inc (working copy) @@ -19,3 +19,4 @@ subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI7420) += pci7420 subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCIXX12) += pcixx12 +subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x Index: src/southbridge/ti/pci1x2x/pci1x2x.c =================================================================== --- src/southbridge/ti/pci1x2x/pci1x2x.c (revision 0) +++ src/southbridge/ti/pci1x2x/pci1x2x.c (working copy) @@ -65,7 +65,7 @@ .scan_bus = 0, }; -#ifdef CONFIG_DRIVERS_TI_PCI1225 +#ifdef CONFIG_SOUTHBRIDGE_TI_PCI1225 static const struct pci_driver ti_pci1225_driver __pci_driver = { .ops = &ti_pci1x2y_ops, .vendor = PCI_VENDOR_ID_TI, @@ -73,14 +73,14 @@ }; #endif -#ifdef CONFIG_DRIVERS_TI_PCI1420 +#ifdef CONFIG_SOUTHBRIDGE_TI_PCI1420 static const struct pci_driver ti_pci1420_driver __pci_driver = { .ops = &ti_pci1x2y_ops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1420, }; #endif -#ifdef CONFIG_DRIVERS_TI_PCI1520 +#ifdef CONFIG_SOUTHBRIDGE_TI_PCI1520 static const struct pci_driver ti_pci1520_driver __pci_driver = { .ops = &ti_pci1x2y_ops, .vendor = PCI_VENDOR_ID_TI, Property changes on: src/southbridge/ti/pci1x2x/pci1x2x.c ___________________________________________________________________ Added: svn:mergeinfo Index: src/southbridge/ti/pci1x2x/Kconfig =================================================================== --- src/southbridge/ti/pci1x2x/Kconfig (revision 0) +++ src/southbridge/ti/pci1x2x/Kconfig (revision 0) @@ -0,0 +1,15 @@ +config SOUTHBRIDGE_TI_PCI1X2X + bool + +config SOUTHBRIDGE_TI_PCI1225 + select SOUTHBRIDGE_TI_PCI1X2X + bool + +config SOUTHBRIDGE_TI_PCI1420 + select SOUTHBRIDGE_TI_PCI1X2X + bool + +config SOUTHBRIDGE_TI_PCI1520 + select SOUTHBRIDGE_TI_PCI1X2X + bool + Index: src/southbridge/ti/pci1x2x/Makefile.inc =================================================================== --- src/southbridge/ti/pci1x2x/Makefile.inc (revision 0) +++ src/southbridge/ti/pci1x2x/Makefile.inc (working copy) @@ -1,2 +1,2 @@ -driver-$(CONFIG_DRIVERS_TI) += ti-pcmcia-cardbus.o +driver-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x.o Property changes on: src/southbridge/ti/pci1x2x/Makefile.inc ___________________________________________________________________ Added: svn:mergeinfo Index: src/include/device/pci_ids.h =================================================================== --- src/include/device/pci_ids.h (revision 5619) +++ src/include/device/pci_ids.h (working copy) @@ -696,7 +696,7 @@ #define PCI_DEVICE_ID_TI_4410 0xac41 #define PCI_DEVICE_ID_TI_4451 0xac42 #define PCI_DEVICE_ID_TI_1420 0xac51 -#define PCI_DEVICE_ID_TI_1520 0xAC55 +#define PCI_DEVICE_ID_TI_1520 0xac55 #define PCI_VENDOR_ID_SONY 0x104d #define PCI_DEVICE_ID_SONY_CXD3222 0x8039 @@ -1742,9 +1742,9 @@ #define PCI_DEVICE_ID_CCD_B00C 0xb00c #define PCI_DEVICE_ID_CCD_B100 0xb100 -#define PCI_VENDOR_ID_NOKIA 0x13B8 // Nokia Telecommunications oy -#define PCI_VENDOR_ID_NOKIA_WIRELESS 0x1603 // Nokia Wireless Communications -#define PCI_VENDOR_ID_NOKIA_HOME 0x1622 // Nokia Home Communications +#define PCI_VENDOR_ID_NOKIA 0x13B8 +#define PCI_VENDOR_ID_NOKIA_WIRELESS 0x1603 +#define PCI_VENDOR_ID_NOKIA_HOME 0x1622 #define PCI_VENDOR_ID_3WARE 0x13C1 #define PCI_DEVICE_ID_3WARE_1000 0x1000 Index: src/mainboard/nokia/ip530/Kconfig =================================================================== --- src/mainboard/nokia/ip530/Kconfig (revision 5619) +++ src/mainboard/nokia/ip530/Kconfig (working copy) @@ -24,8 +24,8 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO - select DRIVERS_TI_PCI1225 - select DRIVERS_DEC_21143PD + select SOUTHBRIDGE_TI_PCI1225 + select SOUTHBRIDGE_DEC_21143 select BOARD_ROMSIZE_KB_256 select ROMCC select PIRQ_ROUTE Index: src/drivers/Kconfig =================================================================== --- src/drivers/Kconfig (revision 5619) +++ src/drivers/Kconfig (working copy) @@ -23,21 +23,3 @@ help It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it. - -config DRIVERS_TI - bool - -config DRIVERS_TI_PCI1225 - select DRIVERS_TI - bool - -config DRIVERS_TI_PCI1420 - select DRIVERS_TI - bool - -config DRIVERS_TI_PCI1520 - select DRIVERS_TI - bool - -config DRIVERS_DEC_21143PD - bool Index: src/drivers/dec/21143/21143pd.c =================================================================== --- src/drivers/dec/21143/21143pd.c (revision 5619) +++ src/drivers/dec/21143/21143pd.c (working copy) @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Bertens <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <console/console.h> - -/** - * The following should be set in the mainboard-specific Kconfig file. - */ -#if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \ - !defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \ - !defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION)) -#error "you must supply these values in your mainboard-specific Kconfig file" -#endif - -/* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */ -/* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */ -/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */ - -/** - * This driver take the values from Kconfig and load them in the registers - */ -static void dec_21143pd_enable( device_t dev ) -{ - printk( BIOS_DEBUG, "Init of DECchip 21143PD/TD Kconfig style\n"); - // Command and Status Configuration Register (Offset 0x04) - pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION ); - printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) ); - // Cache Line Size Register (Offset 0x0C) - pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE ); - printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) ); - // Expansion ROM Base Address Register (Offset 0x30) - pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS ); - printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) ); - return; -} - -static struct device_operations dec_21143pd_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = dec_21143pd_enable, - .scan_bus = 0, -}; - -static const struct pci_driver dec_21143pd_driver __pci_driver = { - .ops = &dec_21143pd_ops, - .vendor = PCI_VENDOR_ID_DEC, - .device = PCI_DEVICE_ID_DEC_21142, -}; Index: src/drivers/dec/21143/Makefile.inc =================================================================== --- src/drivers/dec/21143/Makefile.inc (revision 5619) +++ src/drivers/dec/21143/Makefile.inc (working copy) @@ -1,2 +0,0 @@ -driver-$(CONFIG_DRIVERS_DEC_21143PD) += 21143pd.o - Index: src/drivers/ti/pcmcia-cardbus/Makefile.inc =================================================================== --- src/drivers/ti/pcmcia-cardbus/Makefile.inc (revision 5619) +++ src/drivers/ti/pcmcia-cardbus/Makefile.inc (working copy) @@ -1,2 +0,0 @@ -driver-$(CONFIG_DRIVERS_TI) += ti-pcmcia-cardbus.o - Index: src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c =================================================================== --- src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c (revision 5619) +++ src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c (working copy) @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Bertens <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <console/console.h> - -#if ( !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) ) -#error "you must supply these values in your mainboard-specific Kconfig file" -#endif - -static void ti_pci1x2y_init(struct device *dev) -{ - printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); - // Command register (offset 04) - pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR ); - // Cache Line Size Register (offset 0x0C) - pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR ); - // CardBus latency timer register (offset 1B) - pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR ); - // Bridge control register (offset 3E) - pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR ); - /** Enable change sub-vendor id - * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */ - pci_write_config32( dev, 0x80, 0x10 ); - pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA ); - // Now write the correct value for SCR - // System Control Register (offset 0x80) - pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR ); - // Multifunction routing register - pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR ); - // Set Device Control Register (0x92) accordingly - pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 ); - return; -} - -static struct device_operations ti_pci1x2y_ops = { - .read_resources = NULL, //pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ti_pci1x2y_init, - .scan_bus = 0, -}; - -#ifdef CONFIG_DRIVERS_TI_PCI1225 -static const struct pci_driver ti_pci1225_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, - .vendor = PCI_VENDOR_ID_TI, - .device = PCI_DEVICE_ID_TI_1225, -}; - -#endif -#ifdef CONFIG_DRIVERS_TI_PCI1420 -static const struct pci_driver ti_pci1420_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, - .vendor = PCI_VENDOR_ID_TI, - .device = PCI_DEVICE_ID_TI_1420, -}; -#endif -#ifdef CONFIG_DRIVERS_TI_PCI1520 -static const struct pci_driver ti_pci1520_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, - .vendor = PCI_VENDOR_ID_TI, - .device = PCI_DEVICE_ID_TI_1420, -}; -#endif - -
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