Author: zbao Date: Sat Jun 19 08:55:17 2010 New Revision: 5634 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5634
Log: Trivial. Cleaning up about the blank line. Signed-off-by: Zheng Bao <[email protected]> Acked-by: Zheng Bao <[email protected]> Modified: trunk/src/southbridge/amd/sb700/sb700.c trunk/src/southbridge/amd/sb700/sb700_lpc.c trunk/src/southbridge/amd/sb700/sb700_sm.c trunk/src/southbridge/amd/sb700/sb700_usb.c Modified: trunk/src/southbridge/amd/sb700/sb700.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.c Thu Jun 17 18:16:56 2010 (r5633) +++ trunk/src/southbridge/amd/sb700/sb700.c Sat Jun 19 08:55:17 2010 (r5634) @@ -120,21 +120,21 @@ printk(BIOS_DEBUG, "sb700_enable()\n"); -/* -* 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 -* 0:12.0 OHCI0-USB1 bit 0 of sm_dev 0x68 -* 0:12.1 OHCI1-USB1 bit 1 of sm_dev 0x68 -* 0:12.2 EHCI-USB1 bit 2 of sm_dev 0x68 -* 0:13.0 OHCI0-USB2 bit 4 of sm_dev 0x68 -* 0:13.1 OHCI1-USB2 bit 5 of sm_dev 0x68 -* 0:13.2 EHCI-USB2 bit 6 of sm_dev 0x68 -* 0:14.5 OHCI0-USB3 bit 7 of sm_dev 0x68 -* 0:14.0 SMBUS 0 -* 0:14.1 IDE 1 -* 0:14.2 HDA bit 3 of pm_io 0x59 : 1 - enable, default + 32 * 4 -* 0:14.3 LPC bit 20 of sm_dev 0x64 : 0 - disable, default + 32 * 1 -* 0:14.4 PCI 4 -*/ + /* + * 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 + * 0:12.0 OHCI0-USB1 bit 0 of sm_dev 0x68 + * 0:12.1 OHCI1-USB1 bit 1 of sm_dev 0x68 + * 0:12.2 EHCI-USB1 bit 2 of sm_dev 0x68 + * 0:13.0 OHCI0-USB2 bit 4 of sm_dev 0x68 + * 0:13.1 OHCI1-USB2 bit 5 of sm_dev 0x68 + * 0:13.2 EHCI-USB2 bit 6 of sm_dev 0x68 + * 0:14.5 OHCI0-USB3 bit 7 of sm_dev 0x68 + * 0:14.0 SMBUS 0 + * 0:14.1 IDE 1 + * 0:14.2 HDA bit 3 of pm_io 0x59 : 1 - enable, default + 32 * 4 + * 0:14.3 LPC bit 20 of sm_dev 0x64 : 0 - disable, default + 32 * 1 + * 0:14.4 PCI 4 + */ if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; @@ -143,6 +143,7 @@ vendorid = dev->vendor; deviceid = dev->device; } + bus_dev = dev->bus->dev; if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) && (bus_dev->device == PCI_DEVICE_ID_ATI_SB700_PCI)) { @@ -156,7 +157,6 @@ case 5 << 3: ; } - return; } Modified: trunk/src/southbridge/amd/sb700/sb700_lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_lpc.c Thu Jun 17 18:16:56 2010 (r5633) +++ trunk/src/southbridge/amd/sb700/sb700_lpc.c Sat Jun 19 08:55:17 2010 (r5634) @@ -58,7 +58,6 @@ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); - } static void sb700_lpc_read_resources(device_t dev) @@ -100,7 +99,6 @@ /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, 0xA0); pci_write_config32(dev, 0xA0, res->base | 1 << 1); - } /** Modified: trunk/src/southbridge/amd/sb700/sb700_sm.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_sm.c Thu Jun 17 18:16:56 2010 (r5633) +++ trunk/src/southbridge/amd/sb700/sb700_sm.c Sat Jun 19 08:55:17 2010 (r5634) @@ -72,7 +72,6 @@ dword |= 1 << 13; pci_write_config16(dev, 0x64, dword); - /* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */ /* rpr 2.1 Enabling Legacy Interrupt */ dword = pci_read_config8(dev, 0x62); @@ -282,6 +281,7 @@ return do_smbus_write_byte(res->base, device, address, val); } + static struct smbus_bus_operations lops_smbus_bus = { .recv_byte = lsmbus_recv_byte, .send_byte = lsmbus_send_byte, @@ -335,10 +335,9 @@ res->gran = 8; res->flags = IORESOURCE_IO | IORESOURCE_FIXED; - compact_resources(dev); - } + static void sb700_sm_set_resources(struct device *dev) { struct resource *res; @@ -346,7 +345,6 @@ pci_dev_set_resources(dev); - /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ byte = pm_ioread(0x52); byte |= 1 << 6; @@ -365,6 +363,7 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; + static struct device_operations smbus_ops = { .read_resources = sb700_sm_read_resources, .set_resources = sb700_sm_set_resources, @@ -374,6 +373,7 @@ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; + static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_ATI, Modified: trunk/src/southbridge/amd/sb700/sb700_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_usb.c Thu Jun 17 18:16:56 2010 (r5633) +++ trunk/src/southbridge/amd/sb700/sb700_usb.c Sat Jun 19 08:55:17 2010 (r5634) @@ -42,7 +42,6 @@ byte |= 0xFF; pci_write_config8(sm_dev, 0x68, byte); - /* RPR 6.2 Enables the USB PME Event,Enable USB resume support */ byte = pm_ioread(0x61); byte |= 1 << 6; @@ -188,7 +187,6 @@ set_ehci_base(base); report_resource_stored(dev, res, ""); #endif - } static struct device_operations usb_ops = { @@ -205,6 +203,7 @@ .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, }; + static const struct pci_driver usb_1_driver __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_ATI, -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
