Hi All, Nils wrote: >Peter wrote: >>Nils wrote: >>> +++ src/cpu/amd/model_gx2/cache_as_ram.inc (revision 0) >>.. >>> + post_code(0xc5) >>> +DCacheSetupBad: >>> + hlt /* issues */ >>> + jmp DCacheSetupBad >> >>Should this maybe fail more loudly than a POST code, which can be >>disbled completely. Would be nice to say something on serial. > >I would like that but that`s how it is in Geode LX. >I try if can do a follow up patch for that after this is in. OK?
I spent some time trying to get a debug message printed here but i am probably to stupid. I tried with printk and print_debug but the assembler complained. Could someone perhaps point me to an example in another assembler file? I could not find one. Thanks,Nils. -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
