Hi,
I can not be sure about that because of this firmware trap feature of the chipsets I mention. So are those firmware traps in the SIS chipsets are effective on the boot process of the processor? Or any other reasons?
I think they are independent of CPU itself. It usually configures some registers in chipsets for default values, like SB-NB bus.
If you cannot see any fetches except those, the CPU is not running or is unable to talk to the flash (defective route).
The thermtrip is sw independent so does not play role here. Thanks Rudolf -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
