My chipset is Intel Core2Due/945/ICH7. I have 3 questions.
First question: I wonder how PCI memory read cycles can read an instruction from F000:FFF0 right after reset which is the first instruction of BIOS. Does Coreboot writes into PCI configuration space of Device 31 of ICH7-south bridge(LPC controller)? before initializing the configuration space of Device 0 of 82945(which is memory controller)? I mean the hardware immediately accesses BIOS chip after reset but at some point all memory read/write cycles are claimed by 945 and memory controller? Second question: What is the code flow of Coreboot? Where does it start? and how it contines? Third question: Inside src/mainboard/kontron/986lcd- m/acpi we have some asl files. What language they have been written in? Like superio.asl
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
