Author: stepan Date: Thu Jul 8 02:37:23 2010 New Revision: 5659 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5659
Log: get rid of even more fam10 and k8 warnings. Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Deleted: trunk/src/northbridge/amd/amdmct/mct/mct_fd.c Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore_id.c trunk/src/include/cpu/amd/multicore.h trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c trunk/src/northbridge/amd/amdfam10/setup_resource_map.c trunk/src/northbridge/amd/amdmct/mct/mct.h trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c trunk/src/southbridge/amd/amd8111/amd8111.h trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore_id.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/dualcore/dualcore_id.c Thu Jul 8 02:37:23 2010 (r5659) @@ -14,7 +14,7 @@ return ( ( msr.hi >> (54-32)) & 1); } -static inline unsigned get_initial_apicid(void) +u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xf); } Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Jul 8 02:37:23 2010 (r5659) @@ -252,12 +252,11 @@ printk(BIOS_DEBUG, "\n"); } -static void allow_all_aps_stop(u32 bsp_apicid) +void allow_all_aps_stop(u32 bsp_apicid) { /* Called by the BSP to indicate AP can stop */ - /* FIXME Do APs use this? - Looks like wait_till_sysinfo_in_ram is used instead. */ + /* FIXME Do APs use this? */ // allow aps to stop use 6 bits for state lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14); @@ -395,15 +394,11 @@ } #endif - /* AP is ready, Wait for the BSP to get memory configured */ - /* FIXME: many cores spinning on node0 pci register seems to be bad. - * Why do we need to wait? These APs are just going to go sit in a hlt. - */ - //wait_till_sysinfo_in_ram(); - + /* AP is ready, configure MTRRs and go to sleep */ set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); STOP_CAR_AND_CPU(); + printk(BIOS_DEBUG, "\nAP %02x should be halted but you are reading this....\n", apicid); @@ -912,6 +907,7 @@ printk(BIOS_DEBUG, " done\n"); } +#ifdef UNUSED_CODE static void cpuInitializeMCA(void) { /* Clears Machine Check Architecture (MCA) registers, which power on @@ -939,6 +935,7 @@ } } } +#endif /** * finalize_node_setup() Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Jul 8 02:37:23 2010 (r5659) @@ -191,7 +191,7 @@ printk(BIOS_DEBUG, "\n"); } -static void allow_all_aps_stop(u32 bsp_apicid) +void allow_all_aps_stop(u32 bsp_apicid) { // allow aps to stop Modified: trunk/src/cpu/amd/quadcore/quadcore_id.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore_id.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/quadcore/quadcore_id.c Thu Jul 8 02:37:23 2010 (r5659) @@ -32,7 +32,7 @@ return ( ( msr.hi >> (54-32)) & 1); } -static u32 get_initial_apicid(void) +u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xff); } @@ -67,10 +67,12 @@ return id; } +#ifdef UNUSED_CODE static u32 get_core_num(void) { return (cpuid_ecx(0x80000008) & 0xff); } +#endif static struct node_core_id get_node_core_id_x(void) { Modified: trunk/src/include/cpu/amd/multicore.h ============================================================================== --- trunk/src/include/cpu/amd/multicore.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/include/cpu/amd/multicore.h Thu Jul 8 02:37:23 2010 (r5659) @@ -41,6 +41,8 @@ #else void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); +void allow_all_aps_stop(u32 bsp_apicid); #endif +u32 get_initial_apicid(void); #endif /* CPU_AMD_QUADCORE_H */ Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h Thu Jul 8 02:37:23 2010 (r5659) @@ -1169,8 +1169,16 @@ #endif -#ifndef __ROMCC__ +#ifdef __PRE_RAM__ void showallroutes(int level, device_t dev); + +void setup_resource_map_offset(const u32 *register_values, u32 max, u32 + offset_pci_dev, u32 offset_io_base); + +void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 + offset_pci_dev, u32 offset_io_base); + +void setup_resource_map_x(const u32 *register_values, u32 max); #endif #endif /* AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Thu Jul 8 02:37:23 2010 (r5659) @@ -111,8 +111,6 @@ //#include "../amdmct/mct/mctardk5.c" #endif -#include "../amdmct/mct/mct_fd.c" - #endif /* DDR2 */ int mctRead_SPD(u32 smaddr, u32 reg) Modified: trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Thu Jul 8 02:37:23 2010 (r5659) @@ -28,7 +28,7 @@ pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword); } - +#ifdef UNUSED_CODE static u32 get_htic_bit(u8 i, u8 bit) { u32 dword; @@ -47,6 +47,7 @@ if(get_htic_bit(0, 9)) return; } } +#endif static void set_sysinfo_in_ram(u32 val) { Modified: trunk/src/northbridge/amd/amdfam10/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/setup_resource_map.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/setup_resource_map.c Thu Jul 8 02:37:23 2010 (r5659) @@ -41,9 +41,7 @@ } -static void setup_resource_map_offset(const u32 *register_values, - u32 max, u32 offset_pci_dev, - u32 offset_io_base) +void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; // print_debug("setting up resource map offset...."); @@ -66,8 +64,7 @@ #define RES_PORT_IO_32 0x20 #define RES_MEM_IO 0x40 -static void setup_resource_map_x_offset(const u32 *register_values, u32 max, - u32 offset_pci_dev, u32 offset_io_base) +void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; @@ -133,7 +130,8 @@ print_debug("done.\n"); #endif } -static void setup_resource_map_x(const u32 *register_values, u32 max) + +void setup_resource_map_x(const u32 *register_values, u32 max) { u32 i; Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/mct/mct.h Thu Jul 8 02:37:23 2010 (r5659) @@ -538,7 +538,6 @@ void K8FECCInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -unsigned amd_FD_support(void); void amd_MCTInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); Modified: trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Thu Jul 8 02:37:23 2010 (r5659) @@ -375,7 +375,7 @@ *enabled = 0; } - +#ifdef UNUSED_CODE static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) { u32 tmp; @@ -387,6 +387,7 @@ } return 0; } +#endif void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c Thu Jul 8 02:37:23 2010 (r5659) @@ -70,13 +70,12 @@ return MaxValue; } - - +#ifdef UNUSED_CODE static u8 mct_AdjustFinalDQSRcvValue_1Pass(u8 val_1p, u8 val_2p) { return (val_1p & 0xff) + ((val_2p & 0xff)<<8); } - +#endif u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass) { Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Thu Jul 8 02:37:23 2010 (r5659) @@ -337,6 +337,7 @@ static void coreDelay (void); +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ /* Erratum 350 */ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { @@ -398,6 +399,7 @@ coreDelay(); } +#endif static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Modified: trunk/src/southbridge/amd/amd8111/amd8111.h ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/southbridge/amd/amd8111/amd8111.h Thu Jul 8 02:37:23 2010 (r5659) @@ -5,4 +5,8 @@ void amd8111_enable(device_t dev); +#ifdef __PRE_RAM__ +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif + #endif /* AMD8111_H */ Modified: trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Thu Jul 8 02:37:23 2010 (r5659) @@ -1,3 +1,4 @@ +#include "amd8111.h" #include <reset.h> /* by yhlu 2005.10 */ @@ -45,7 +46,7 @@ outb(0x0e, 0x0cf9); // make sure cf9 is enabled } -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { device_t dev; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
