Hi. I have a Jetway 7F4K1G5S-LF board I'm trying to get working.
When I build coreboot using the J7f24 target, it doesn't get past "doing early_mtrr".
I added a few print statements (and included console.h) to try to track it down, and in "include/cpu/x86/cache.h" in disable_cache it will print the statement before
write_cr0(cr0); but not the one after it. I don't know what to try next. I'm doing this on a 32-bit sidux box, with gcc 4.4.4. Any ideas? Thanks, Rob Austin -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot

