On Wed, Aug 11, 2010 at 12:15 PM, Votier, Sean (DS-1) <[email protected]> wrote: > I’ve been on and off the list for a few months. My email system doesn’t seem > to like list traffic so it’s a bit touch and go so I will have to see how > long it lasts. It’s been interesting reading but now I have a question…. > > I’m writing some BIOS code for the I7520 chipset. In general, with these > chipsets is there some basic legacy I/O mapping for parallel, serial and > other real mode devices by default on power up? I’m hoping that something > similar happens to the way that the Firmware Hub is made to look like a BIOS > rom on power up. I need to read one GPIO pin very early in the bios > initialisation and hope I can just look at a bit at I/O address 378.
I don't have any chipset-specific information, but here are a couple of thoughts: - Is there a Super IO chip? Generally the Super IO chip handles serial & has some GPIO pins. - To allow the Super IO to function correctly, the IO there is often subtractively decoded (if the chipset doesn't claim an address, it passes it on.) - I would think that there would be a register in the PCI space for the chipset that controls the address of the GPIO pins. Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
