Author: stepan Date: Tue Aug 17 17:19:32 2010 New Revision: 5718 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5718
Log: Commit (non-working!) Jetway PA78VM5 mainboard Signed-off-by: Wang Qing Pei <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Added: trunk/src/mainboard/jetway/pa78vm5/ - copied from r5716, trunk/src/mainboard/amd/tilapia_fam10/ Deleted: trunk/src/mainboard/jetway/pa78vm5/mb_sysconf.h trunk/src/mainboard/jetway/pa78vm5/spd_addr.h Modified: trunk/src/mainboard/jetway/Kconfig trunk/src/mainboard/jetway/pa78vm5/Kconfig trunk/src/mainboard/jetway/pa78vm5/acpi/routing.asl trunk/src/mainboard/jetway/pa78vm5/acpi/sata.asl trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c trunk/src/mainboard/jetway/pa78vm5/chip.h trunk/src/mainboard/jetway/pa78vm5/devicetree.cb trunk/src/mainboard/jetway/pa78vm5/dsdt.asl trunk/src/mainboard/jetway/pa78vm5/mainboard.c trunk/src/mainboard/jetway/pa78vm5/mptable.c trunk/src/mainboard/jetway/pa78vm5/resourcemap.c trunk/src/mainboard/jetway/pa78vm5/romstage.c Modified: trunk/src/mainboard/jetway/Kconfig ============================================================================== --- trunk/src/mainboard/jetway/Kconfig Tue Aug 17 17:05:05 2010 (r5717) +++ trunk/src/mainboard/jetway/Kconfig Tue Aug 17 17:19:32 2010 (r5718) @@ -3,6 +3,6 @@ depends on VENDOR_JETWAY source "src/mainboard/jetway/j7f24/Kconfig" - +source "src/mainboard/jetway/pa78vm5/Kconfig" endchoice Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/Kconfig Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/Kconfig Tue Aug 17 17:19:32 2010 (r5718) @@ -1,11 +1,11 @@ -config BOARD_AMD_TILAPIA_FAM10 - bool "Tilapia (Fam10)" +config BOARD_JETWAY_PA78VM5 + bool "PA78VM5 (Fam10)" select ARCH_X86 - select CPU_AMD_SOCKET_AM3 + select CPU_AMD_SOCKET_AM2R2 select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_ITE_IT8718F + select SUPERIO_FINTEK_F71863FG select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE @@ -26,100 +26,100 @@ config MAINBOARD_DIR string - default amd/tilapia_fam10 - depends on BOARD_AMD_TILAPIA_FAM10 + default jetway/pa78vm5 + depends on BOARD_JETWAY_PA78VM5 config APIC_ID_OFFSET hex default 0x0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config MAINBOARD_PART_NUMBER string - default "Tilapia (Fam10)" - depends on BOARD_AMD_TILAPIA_FAM10 + default "PA78VM5 (Fam10)" + depends on BOARD_JETWAY_PA78VM5 config HW_MEM_HOLE_SIZEK hex default 0x100000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config MAX_CPUS int default 8 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config MAX_PHYSICAL_CPUS int default 2 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config HW_MEM_HOLE_SIZE_AUTO_INC bool default n - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config MEM_TRAIN_SEQ int default 2 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config SB_HT_CHAIN_ON_BUS0 int default 1 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config HT_CHAIN_END_UNITID_BASE hex default 0x1 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config HT_CHAIN_UNITID_BASE hex default 0x0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config IRQ_SLOT_COUNT int default 11 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config AMD_UCODE_PATCH_FILE string default "mc_patch_010000b6.h" - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config RAMTOP hex default 0x2000000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config HEAP_SIZE hex default 0xc0000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config ACPI_SSDTX_NUM int default 0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x1022 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config RAMBASE hex default 0x200000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 config COMPRESS hex default 0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_JETWAY_PA78VM5 Modified: trunk/src/mainboard/jetway/pa78vm5/acpi/routing.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi/routing.asl Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/acpi/routing.asl Tue Aug 17 17:19:32 2010 (r5718) @@ -62,16 +62,21 @@ /* SB devices */ /* Bus 0, Dev 17 - SATA controller #2 */ /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 1, INTA, 0 }, + Package(){0x0011FFFF, 0, INTA, 0 }, - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ Package(){0x0012FFFF, 0, INTA, 0 }, Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTA, 0 }, + Package(){0x0012FFFF, 2, INTC, 0 }, - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTD, 0 }, + Package(){0x0013FFFF, 2, INTA, 0 }, + + /* Package(){0x0014FFFF, 1, INTA, 0 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, Package(){0x0014FFFF, 2, INTC, 0 }, @@ -136,16 +141,22 @@ /* Bus 0, Dev 18 - SATA controller #1 */ Package(){0x0011FFFF, 0, 0, 22 }, - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ Package(){0x0012FFFF, 0, 0, 16 }, Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0012FFFF, 2, 0, 18 }, + Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0013FFFF, 2, 0, 16 }, + + /* Package(){0x00140000, 0, 0, 16 }, */ + /* Package(){0x00130004, 2, 0, 18 }, */ /* Package(){0x00130005, 3, 0, 19 }, */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, Modified: trunk/src/mainboard/jetway/pa78vm5/acpi/sata.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi/sata.asl Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/acpi/sata.asl Tue Aug 17 17:19:32 2010 (r5718) @@ -23,7 +23,7 @@ Scope (_SB) { Device(PCI0) { Device(SATA) { - Name(_ADR, 0x00110000) + Name(_ADR, 0x00120000) #include "sata.asl" } } Modified: trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c Tue Aug 17 17:19:32 2010 (r5718) @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2010 Wang Qing Pei <[email protected]> * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -26,8 +27,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> -#include "mb_sysconf.h" - #define DUMP_ACPI_TABLES 0 #if DUMP_ACPI_TABLES == 1 Modified: trunk/src/mainboard/jetway/pa78vm5/chip.h ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/chip.h Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/chip.h Tue Aug 17 17:19:32 2010 (r5718) @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2010 Wang Qing Pei <[email protected]> * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -21,6 +22,4 @@ extern struct chip_operations mainboard_ops; struct mainboard_config { -// int fixup_scsi; -// int fixup_vga; }; Modified: trunk/src/mainboard/jetway/pa78vm5/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/devicetree.cb Tue Aug 17 17:19:32 2010 (r5718) @@ -1,7 +1,7 @@ -# sample config for amd/tilapia_fam10 +# sample config for jetway/PA78VM5 chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 + chip cpu/amd/socket_AM2r2 #L1 and DDR2 device lapic 0 on end end end @@ -24,8 +24,7 @@ register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" - + register "gfx_dual_slot" = "1" register "gfx_lane_reversal" = "0" register "gfx_tmds" = "0" register "gfx_compliance" = "0" @@ -57,7 +56,7 @@ device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f + chip superio/fintek/f71863fg device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -115,31 +114,5 @@ end end #pci_domain #for node 32 to node 63 -# device pci_domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end end Modified: trunk/src/mainboard/jetway/pa78vm5/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/dsdt.asl Tue Aug 17 17:19:32 2010 (r5718) @@ -22,8 +22,8 @@ "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "TILAPIA ", /* TABLE ID */ + "JETWAY", /* OEMID */ + "PA78VM5 ", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -313,7 +313,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, Modified: trunk/src/mainboard/jetway/pa78vm5/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mainboard.c Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/mainboard.c Tue Aug 17 17:19:32 2010 (r5718) @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2010 Wang Qing Pei <[email protected]> * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -28,83 +29,47 @@ #include <southbridge/amd/sb700/sb700.h> #include "chip.h" -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ - -extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); - -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) - #define SMBUS_IO_BASE 0x6000 uint64_t uma_memory_base, uma_memory_size; void set_pcie_dereset(void); void set_pcie_reset(void); -u8 is_dev3_present(void); +/* + * the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to + * pull it up before training the slot. + ***/ void set_pcie_dereset() { - u8 byte; u16 word; device_t sm_dev; - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 1 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte |= ((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 1 */ + /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x7e); - word |= (1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); + + word = pci_read_config16(sm_dev, 0xA8); + word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ + word &= ~((1 << 8) | (1 << 10)); + pci_write_config16(sm_dev, 0xA8, word); } void set_pcie_reset() { - u8 byte; u16 word; device_t sm_dev; - - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 0 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte &= ~((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 0 */ + /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x7e); - word &= ~(1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); + + word = pci_read_config16(sm_dev, 0xA8); + word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ + word &= ~((1 << 8) | (1 << 10)); + pci_write_config16(sm_dev, 0xA8, word); } -#if 0 /* TODO: */ +#if 0 /* not tested yet. */ /******************************************************** -* tilapia uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to +* board uses SB700 GPIO9 to detect IDE_DMA66. +* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to * get the cable type, 40 pin or 80 pin? ********************************************************/ static void get_ide_dma66(void) @@ -116,195 +81,48 @@ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ + byte |= (1 << 5); /* Set Gpio9 as input */ pci_write_config8(sm_dev, 0xA9, byte); ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) byte |= 2 << 0; /* mode 2 */ else byte |= 5 << 0; /* mode 5 */ pci_write_config8(ide_dev, 0x56, byte); } -#endif - -/* - * justify the dev3 is exist or not - */ -u8 is_dev3_present(void) -{ - u16 word; - device_t sm_dev; - - /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - /* put the GPIO68 output to tristate */ - word = pci_read_config16(sm_dev, 0x7e); - word |= 1 << 6; - pci_write_config16(sm_dev, 0x7e,word); - - /* read the GPIO68 input status */ - word = pci_read_config16(sm_dev, 0x7e); - - if(word & (1 << 10)){ - /*not exist*/ - return 0; - }else{ - /*exist*/ - return 1; - } -} - - -/* - * set gpio40 gfx - */ -static void set_gpio40_gfx(void) -{ - u8 byte; - u32 dword; - device_t sm_dev; - /* disable the GPIO40 as CLKREQ2# function */ - byte = pm_ioread(0xd3); - byte &= ~(1 << 7); - pm_iowrite(0xd3, byte); - - /* disable the GPIO40 as CLKREQ3# function */ - byte = pm_ioread(0xd4); - byte &= ~(1 << 0); - pm_iowrite(0xd4, byte); - - /* enable pull up for GPIO68 */ - byte = pm2_ioread(0xf1); - byte &= ~(1 << 4); - pm2_iowrite(0xf1, byte); - - /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - /*if the dev3 is present, set the gfx to 2x8 lanes*/ - /*otherwise set the gfx to 1x16 lanes*/ - if(is_dev3_present()){ - - printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword |= (1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - - }else{ - printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword &= ~(1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - } -} - -/* - * set thermal config - */ -static void set_thermal_config(void) -{ - u8 byte; - u16 word; - device_t sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); - - /* sb700 settings for thermal config */ - /* set SB700 GPIO 64 to GPIO with pull-up */ - byte = pm2_ioread(0x42); - byte &= 0x3f; - pm2_iowrite(0x42, byte); - - /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x56); - word |= 1 << 7; - pci_write_config16(sm_dev, 0x56, word); - - /* set GPIO 64 internal pull-up */ - byte = pm2_ioread(0xf0); - byte &= 0xee; - pm2_iowrite(0xf0, byte); - - /* set Talert to be active low */ - byte = pm_ioread(0x67); - byte &= ~(1 << 5); - pm_iowrite(0x67, byte); - - /* set Talert to generate ACPI event */ - byte = pm_ioread(0x3c); - byte &= 0xf3; - pm_iowrite(0x3c, byte); - - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ -} +#endif /* get_ide_dma66() */ /************************************************* -* enable the dedicated function in tilapia board. +* enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void tilapia_enable(device_t dev) +static void pa78vm5_enable(device_t dev) { /* Leave it for furture use. */ /* struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; */ - printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", __func__, msr.lo, msr.hi); /* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", __func__, msr2.lo, msr2.hi); + /* refer to UMA Size Consideration in 780 BDG. */ switch (msr.lo) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ @@ -331,8 +149,6 @@ set_pcie_dereset(); /* get_ide_dma66(); */ - set_thermal_config(); - set_gpio40_gfx(); } int add_mainboard_resources(struct lb_memory *mem) @@ -350,6 +166,6 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD TILAPIA Mainboard") - .enable_dev = tilapia_enable, + CHIP_NAME("AMD PA78VM5 Mainboard") + .enable_dev = pa78vm5_enable, }; Modified: trunk/src/mainboard/jetway/pa78vm5/mptable.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mptable.c Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/mptable.c Tue Aug 17 17:19:32 2010 (r5718) @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2010 Wang Qing Pei <[email protected]> * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -43,7 +44,7 @@ { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; - static const char productid[12] = "TILAPIA "; + static const char productid[12] = "PA78VM5 "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/jetway/pa78vm5/resourcemap.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/resourcemap.c Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/resourcemap.c Tue Aug 17 17:19:32 2010 (r5718) @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2010 Wang Qing Pei <[email protected]> * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Aug 17 17:19:32 2010 (r5718) @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2010 Wang Qing Pei <[email protected]> * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -59,7 +60,13 @@ static int smbus_read_byte(u32 device, u32 address); -#include "superio/ite/it8718f/it8718f_early_serial.c" +#include "superio/fintek/f71863fg/f71863fg_early_serial.c" +#if CONFIG_TTYS0_BASE == 0x2f8 +#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2) +#else +#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -81,6 +88,7 @@ #include "northbridge/amd/amdfam10/amdfam10.h" + #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" @@ -95,7 +103,7 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" -//#include "spd_addr.h" + #define RC00 0 #define RC01 1 @@ -136,7 +144,7 @@ enable_rs780_dev8(); sb700_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk(BIOS_DEBUG, "\n"); @@ -250,7 +258,6 @@ // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); @@ -261,3 +268,4 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
