Dear coreboot readers! This is the automatic build system of coreboot.
The developer "ruik" checked in revision 5720 to the coreboot repository. This caused the following changes: Change Log: Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and I removed the gpio asserts - I think those are not used here. The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better. The classic PCI slot works fine too. However it seems SATA has some issues. Signed-off-by: Rudolf Marek <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Build Log: Compilation of jetway:pa78vm5 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5720&device=pa78vm5&vendor=jetway&num=2 If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
