Author: stepan Date: Sun Aug 22 21:45:57 2010 New Revision: 5729 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5729
Log: Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc. While reviewing impact of this change it seems code for erratum 531 was not in sync with current docs. I have checked uses of AMD_FAM10_ALL, but I haven't looked up the docs for all of them, at first sight it seems ok to include all FAM10 revisions in this mask. Apply errata 531 only to revisions listed in Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010. Before it was applied also to DR-B0, DA-C3 or HY-D0 which are not affected according to current docs. Signed-off-by: Xavi Drudis Ferran <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/northbridge/amd/amdmct/amddefs.h Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:41:47 2010 (r5728) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:45:57 2010 (r5729) @@ -136,27 +136,27 @@ * program Link Global Extended Control Register[ForceFullT0] * (F0x16C[15:13]) to 000b */ - { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */ + { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, /* FIXME Should include BL_C2 but there is no constant */ 0x00000000, 0x00000100 }, - { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x174, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x178, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x17C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x180, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x184, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x188, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x18C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, /* Link Global Extended Control Register */ - { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x16C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b, * Set T0Time 14h per BKDG */ Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Sun Aug 22 21:41:47 2010 (r5728) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Sun Aug 22 21:45:57 2010 (r5729) @@ -62,10 +62,11 @@ #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_ALL (AMD_DR_Bx) -#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 ) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_DR_Cx (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3) #define AMD_DR_Dx (AMD_HY_D0) +#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) /* -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
