Hello,
Following patch moves the PHY fine tune settings into devicetree.cb. Suited for
AMD SB7xx. Please change the default settings for Gigabyte and Jetway.
Signed-off-by: Rudolf Marek <[email protected]>
Untested I can test on monday evening.
Thanks,
Rudolf
Index: src/southbridge/amd/sb700/sb700_sata.c
===================================================================
--- src/southbridge/amd/sb700/sb700_sata.c.orig 2010-08-22 11:54:20.000000000 +0200
+++ src/southbridge/amd/sb700/sb700_sata.c 2010-08-22 11:54:40.000000000 +0200
@@ -62,9 +62,7 @@
u32 sata_bar5;
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
int i, j;
-
- struct southbridge_ati_sb700_config *conf;
- conf = dev->chip_info;
+ struct southbridge_amd_sb700_config *conf = dev->chip_info;
device_t sm_dev;
/* SATA SMBus Disable */
@@ -167,20 +165,20 @@
pci_write_config16(dev, 0x86, word);
/* RPR7.6.2 SATA GENI PHY ports setting */
- pci_write_config32(dev, 0x88, 0x01B48017);
- pci_write_config32(dev, 0x8c, 0x01B48019);
- pci_write_config32(dev, 0x90, 0x01B48016);
- pci_write_config32(dev, 0x94, 0x01B48016);
- pci_write_config32(dev, 0x98, 0x01B48016);
- pci_write_config32(dev, 0x9C, 0x01B48016);
+ pci_write_config32(dev, 0x88, conf->sphy15_p0);
+ pci_write_config32(dev, 0x8c, conf->sphy15_p1);
+ pci_write_config32(dev, 0x90, conf->sphy15_p2);
+ pci_write_config32(dev, 0x94, conf->sphy15_p3);
+ pci_write_config32(dev, 0x98, conf->sphy15_p4);
+ pci_write_config32(dev, 0x9C, conf->sphy15_p5);
/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
- pci_write_config16(dev, 0xA0, 0xA09A);
- pci_write_config16(dev, 0xA2, 0xA09F);
- pci_write_config16(dev, 0xA4, 0xA07A);
- pci_write_config16(dev, 0xA6, 0xA07A);
- pci_write_config16(dev, 0xA8, 0xA07A);
- pci_write_config16(dev, 0xAA, 0xA07A);
+ pci_write_config16(dev, 0xA0, conf->sphy30_p0);
+ pci_write_config16(dev, 0xA2, conf->sphy30_p1);
+ pci_write_config16(dev, 0xA4, conf->sphy30_p2);
+ pci_write_config16(dev, 0xA6, conf->sphy30_p3);
+ pci_write_config16(dev, 0xA8, conf->sphy30_p4);
+ pci_write_config16(dev, 0xAA, conf->sphy30_p5);
/* Enable the I/O, MM, BusMaster access for SATA */
byte = pci_read_config8(dev, 0x4);
Index: src/southbridge/amd/sb700/chip.h
===================================================================
--- src/southbridge/amd/sb700/chip.h.orig 2010-08-22 11:54:20.000000000 +0200
+++ src/southbridge/amd/sb700/chip.h 2010-08-22 12:12:45.000000000 +0200
@@ -26,6 +26,18 @@
u32 sata0_enable : 1;
u32 boot_switch_sata_ide : 1;
u32 hda_viddid;
+ u32 sphy15_p0;
+ u32 sphy15_p1;
+ u32 sphy15_p2;
+ u32 sphy15_p3;
+ u32 sphy15_p4;
+ u32 sphy15_p5;
+ u32 sphy30_p0;
+ u32 sphy30_p1;
+ u32 sphy30_p2;
+ u32 sphy30_p3;
+ u32 sphy30_p4;
+ u32 sphy30_p5;
};
struct chip_operations;
extern struct chip_operations southbridge_amd_sb700_ops;
Index: src/mainboard/asrock/939a785gmh/devicetree.cb
===================================================================
--- src/mainboard/asrock/939a785gmh/devicetree.cb.orig 2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/asrock/939a785gmh/devicetree.cb 2010-08-22 12:12:45.000000000 +0200
@@ -120,6 +120,19 @@
register "sata0_enable" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "hda_viddid" = "0x10ec0882"
+ # SATA PHY fine tune, depends on PCB layout!
+ register "sphy15_p0" = "0x01b48016"
+ register "sphy15_p1" = "0x01b48016"
+ register "sphy15_p2" = "0x01b48016"
+ register "sphy15_p3" = "0x01b48016"
+ register "sphy15_p4" = "0x01b48016"
+ register "sphy15_p5" = "0x01b48016"
+ register "sphy30_p0" = "0xa07a"
+ register "sphy30_p1" = "0xa07a"
+ register "sphy30_p2" = "0xa07a"
+ register "sphy30_p3" = "0xa07a"
+ register "sphy30_p4" = "0xa07a"
+ register "sphy30_p5" = "0xa0ff"
end #southbridge/amd/sb700
end # device pci 18.0
Index: src/mainboard/gigabyte/ma78gm/devicetree.cb
===================================================================
--- src/mainboard/gigabyte/ma78gm/devicetree.cb.orig 2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/gigabyte/ma78gm/devicetree.cb 2010-08-22 12:12:45.000000000 +0200
@@ -101,6 +101,19 @@
register "sata0_enable" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "hda_viddid" = "0x10ec0882"
+ # SATA PHY fine tune, depends on PCB layout!
+ register "sphy15_p0" = "0x01b48017"
+ register "sphy15_p1" = "0x01b48019"
+ register "sphy15_p2" = "0x01b48016"
+ register "sphy15_p3" = "0x01b48016"
+ register "sphy15_p4" = "0x01b48016"
+ register "sphy15_p5" = "0x01b48016"
+ register "sphy30_p0" = "0xa09a"
+ register "sphy30_p1" = "0xa09f"
+ register "sphy30_p2" = "0xa07a"
+ register "sphy30_p3" = "0xa07a"
+ register "sphy30_p4" = "0xa07a"
+ register "sphy30_p5" = "0xa07a"
end #southbridge/amd/sb700
end # device pci 18.0
Index: src/mainboard/gigabyte/ma785gmt/devicetree.cb
===================================================================
--- src/mainboard/gigabyte/ma785gmt/devicetree.cb.orig 2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/gigabyte/ma785gmt/devicetree.cb 2010-08-22 12:12:45.000000000 +0200
@@ -102,6 +102,19 @@
register "sata0_enable" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "hda_viddid" = "0x10ec0882"
+ # SATA PHY fine tune, depends on PCB layout!
+ register "sphy15_p0" = "0x01b48017"
+ register "sphy15_p1" = "0x01b48019"
+ register "sphy15_p2" = "0x01b48016"
+ register "sphy15_p3" = "0x01b48016"
+ register "sphy15_p4" = "0x01b48016"
+ register "sphy15_p5" = "0x01b48016"
+ register "sphy30_p0" = "0xa09a"
+ register "sphy30_p1" = "0xa09f"
+ register "sphy30_p2" = "0xa07a"
+ register "sphy30_p3" = "0xa07a"
+ register "sphy30_p4" = "0xa07a"
+ register "sphy30_p5" = "0xa07a"
end #southbridge/amd/sb700
end # device pci 18.0
Index: src/mainboard/amd/mahogany/devicetree.cb
===================================================================
--- src/mainboard/amd/mahogany/devicetree.cb.orig 2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/amd/mahogany/devicetree.cb 2010-08-22 12:12:45.000000000 +0200
@@ -110,6 +110,19 @@
register "sata0_enable" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "hda_viddid" = "0x10ec0882"
+ # SATA PHY fine tune, depends on PCB layout!
+ register "sphy15_p0" = "0x01b48017"
+ register "sphy15_p1" = "0x01b48019"
+ register "sphy15_p2" = "0x01b48016"
+ register "sphy15_p3" = "0x01b48016"
+ register "sphy15_p4" = "0x01b48016"
+ register "sphy15_p5" = "0x01b48016"
+ register "sphy30_p0" = "0xa09a"
+ register "sphy30_p1" = "0xa09f"
+ register "sphy30_p2" = "0xa07a"
+ register "sphy30_p3" = "0xa07a"
+ register "sphy30_p4" = "0xa07a"
+ register "sphy30_p5" = "0xa07a"
end #southbridge/amd/sb700
end # device pci 18.0
Index: src/mainboard/amd/mahogany_fam10/devicetree.cb
===================================================================
--- src/mainboard/amd/mahogany_fam10/devicetree.cb.orig 2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/amd/mahogany_fam10/devicetree.cb 2010-08-22 12:12:45.000000000 +0200
@@ -101,6 +101,19 @@
register "sata0_enable" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "hda_viddid" = "0x10ec0882"
+ # SATA PHY fine tune, depends on PCB layout!
+ register "sphy15_p0" = "0x01b48017"
+ register "sphy15_p1" = "0x01b48019"
+ register "sphy15_p2" = "0x01b48016"
+ register "sphy15_p3" = "0x01b48016"
+ register "sphy15_p4" = "0x01b48016"
+ register "sphy15_p5" = "0x01b48016"
+ register "sphy30_p0" = "0xa09a"
+ register "sphy30_p1" = "0xa09f"
+ register "sphy30_p2" = "0xa07a"
+ register "sphy30_p3" = "0xa07a"
+ register "sphy30_p4" = "0xa07a"
+ register "sphy30_p5" = "0xa07a"
end #southbridge/amd/sb700
end # device pci 18.0
Index: src/mainboard/amd/tilapia_fam10/devicetree.cb
===================================================================
--- src/mainboard/amd/tilapia_fam10/devicetree.cb.orig 2010-08-22 11:54:20.000000000 +0200
+++ src/mainboard/amd/tilapia_fam10/devicetree.cb 2010-08-22 12:12:45.000000000 +0200
@@ -102,6 +102,19 @@
register "sata0_enable" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "hda_viddid" = "0x10ec0882"
+ # SATA PHY fine tune, depends on PCB layout!
+ register "sphy15_p0" = "0x01b48017"
+ register "sphy15_p1" = "0x01b48019"
+ register "sphy15_p2" = "0x01b48016"
+ register "sphy15_p3" = "0x01b48016"
+ register "sphy15_p4" = "0x01b48016"
+ register "sphy15_p5" = "0x01b48016"
+ register "sphy30_p0" = "0xa09a"
+ register "sphy30_p1" = "0xa09f"
+ register "sphy30_p2" = "0xa07a"
+ register "sphy30_p3" = "0xa07a"
+ register "sphy30_p4" = "0xa07a"
+ register "sphy30_p5" = "0xa07a"
end #southbridge/amd/sb700
end # device pci 18.0
Index: src/mainboard/jetway/pa78vm5/devicetree.cb
===================================================================
--- src/mainboard/jetway/pa78vm5/devicetree.cb.orig 2010-08-22 12:13:07.000000000 +0200
+++ src/mainboard/jetway/pa78vm5/devicetree.cb 2010-08-22 12:13:16.000000000 +0200
@@ -101,6 +101,19 @@
register "sata0_enable" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "hda_viddid" = "0x10ec0882"
+ # SATA PHY fine tune, depends on PCB layout!
+ register "sphy15_p0" = "0x01b48017"
+ register "sphy15_p1" = "0x01b48019"
+ register "sphy15_p2" = "0x01b48016"
+ register "sphy15_p3" = "0x01b48016"
+ register "sphy15_p4" = "0x01b48016"
+ register "sphy15_p5" = "0x01b48016"
+ register "sphy30_p0" = "0xa09a"
+ register "sphy30_p1" = "0xa09f"
+ register "sphy30_p2" = "0xa07a"
+ register "sphy30_p3" = "0xa07a"
+ register "sphy30_p4" = "0xa07a"
+ register "sphy30_p5" = "0xa07a"
end #southbridge/amd/sb700
end # device pci 18.0
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
