See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [email protected] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
Fix i945 based boards
- prevent GCC from inlining do_ram_command - it will break RAM initialization.
- fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not
200us
- move PCIRST# as early as possible (before ich7_enable_lpc)
Signed-off-by: Stefan Reinauer <[email protected]>
Index: src/northbridge/intel/i945/raminit.c
===================================================================
--- src/northbridge/intel/i945/raminit.c (revision 5739)
+++ src/northbridge/intel/i945/raminit.c (working copy)
@@ -45,7 +45,7 @@
#define RAM_EMRS_2 (0x1 << 21)
#define RAM_EMRS_3 (0x2 << 21)
-static void do_ram_command(u32 command)
+static __attribute__((noinline)) void do_ram_command(u32 command)
{
u32 reg32;
Index: src/mainboard/getac/p470/romstage.c
===================================================================
--- src/mainboard/getac/p470/romstage.c (revision 5739)
+++ src/mainboard/getac/p470/romstage.c (working copy)
@@ -308,9 +308,8 @@
#if 0
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
- udelay(200);
+ udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
- udelay(200);
#endif
ich7_enable_lpc();
Index: src/mainboard/kontron/986lcd-m/romstage.c
===================================================================
--- src/mainboard/kontron/986lcd-m/romstage.c (revision 5739)
+++ src/mainboard/kontron/986lcd-m/romstage.c (working copy)
@@ -366,14 +366,12 @@
enable_lapic();
}
- ich7_enable_lpc();
-
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
- udelay(200);
+ udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
- udelay(200);
+ ich7_enable_lpc();
early_superio_config_w83627thg();
/* Set up the console */
Index: src/mainboard/roda/rk886ex/romstage.c
===================================================================
--- src/mainboard/roda/rk886ex/romstage.c (revision 5739)
+++ src/mainboard/roda/rk886ex/romstage.c (working copy)
@@ -279,11 +279,12 @@
enable_lapic();
}
- ich7_enable_lpc();
-
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+ udelay(200 * 1000);
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
+ ich7_enable_lpc();
early_superio_config();
/* Set up the console */
--
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