I think David Borg might also have looked at this chipset. I attached my patch for the chipset.
-Anders tir, 31 08 2010 kl. 22:57 +0200, skrev Mats Erik Andersson: > lördag den 28 augusti 2010 klockan 13:16 skrev [email protected] detta: > > I did some initial code for this chip set (debug is working) > > but haven't played with it for a while. > > > > Mvh Anders > > > > This is good news, that some knowledge indeed has been > gathered. I will begin reading the more or less relevant > background material there is, so I would welcome any > collaboration that might be offered. > > > Hälsningar, best regards, > > Mats E A > > > ----- Reply message ----- > > Fra: "Darmawan Salihun" <[email protected]> > > Dato: lør., aug. 28, 2010 10:09 > > Emne: [coreboot] Chipset VIA Apollo Pro+? > > Til: "Mats Erik Andersson" <[email protected]> > > Cc: <[email protected]> > > > > > > I have the datasheet of this chipset. I'll send it to you later. I was > > one working with legacy BIOS on moatherboard with this chipset. > > > > -Darmawan > > > > On 8/27/10, Mats Erik Andersson <[email protected]> wrote: > > > Hello, > > > > > > is there now, or has there been, someone interested > > > in the legacy chipset VIA Apollo Pro+? In the sense > > > of investigating its use with Coreboot. > > > > > > The northbridge is VIA VT82C693, and the southbridge > > > is VIA VT82C596A on a mainboard from ECS: > > > > > > PCI-bridge VT82C691, > > > AGP-bridge VT82C598, > > > ISA-bridge VT82C596A, > > > IDE-interface VT82C571, > > > USB-controller VT82C572, and > > > Power-ctrl VT82C596. > > > > > > A search for datasheets has given nothing but trivial > > > information.
Index: src/southbridge/via/Kconfig =================================================================== --- src/southbridge/via/Kconfig (revision 5664) +++ src/southbridge/via/Kconfig (working copy) @@ -1,4 +1,5 @@ source src/southbridge/via/k8t890/Kconfig +source src/southbridge/via/vt82c686/Kconfig source src/southbridge/via/vt8231/Kconfig source src/southbridge/via/vt8235/Kconfig source src/southbridge/via/vt8237r/Kconfig Index: src/southbridge/via/Makefile.inc =================================================================== --- src/southbridge/via/Makefile.inc (revision 5664) +++ src/southbridge/via/Makefile.inc (working copy) @@ -1,5 +1,6 @@ subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M890) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231 +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT82C686) += vt82c686 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8235) += vt8235 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r Index: src/southbridge/via/vt82c686/vt82c686.h =================================================================== --- src/southbridge/via/vt82c686/vt82c686.h (revision 5664) +++ src/southbridge/via/vt82c686/vt82c686.h (working copy) @@ -44,7 +44,7 @@ /* For reference, used PCI IDs and their names in pci_ids.h: */ /* -PCI_VENDOR_ID_VIA 0x1106 +#define PCI_VENDOR_ID_VIA 0x1106 PCI_DEVICE_ID_VIA_82C686 0x0686 // Function 0, PCI Config PCI_DEVICE_ID_VIA_82C586_1 0x0571 // Function 1, IDE Controller PCI_DEVICE_ID_VIA_82C586_2 0x3038 // Functions 2 & 3, USB Ports 0-1 & 2-3 @@ -54,3 +54,10 @@ PCI_DEVICE_ID_VIA_82C686_6 0x3068 // Function 6, MC'97 Codec */ +/* SMBus */ +#define SMBBA 0x90 /* SMBus base address */ +#define SMBHSTCFG 0xd2 /* SMBus host configuration */ + +/* Bit definitions */ +#define SMB_HST_EN (1 << 0) /* Host Interface Enable */ + Index: src/southbridge/via/vt82c686/vt82c686_early_smbus.c =================================================================== --- src/southbridge/via/vt82c686/vt82c686_early_smbus.c (revision 0) +++ src/southbridge/via/vt82c686/vt82c686_early_smbus.c (revision 0) @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <device/smbus_def.h> +#include <stdint.h> +#include <device/pci_ids.h> +#include "vt82c686.h" +//#include "vt82c686_smbus.h" +#define SMBUS_IO_BASE 0xe800 +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBUS_TIMEOUT (100*1000*10) + +static void enable_smbus(void) +{ + device_t dev; + u8 reg8; + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_82C686_4), 0); + + if (dev == PCI_DEV_INVALID) { + die("SMBus controller not found\n"); + } + + /* Set the SMBus I/O base. */ + pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); + + /* Enable the SMBus controller host interface. */ + reg8 = pci_read_config8(dev, SMBHSTCFG); + reg8 |= SMB_HST_EN; + pci_write_config8(dev, SMBHSTCFG, reg8); + + print_spew("SMBus controller enabled\n"); +} + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +static int smbus_wait_until_active(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1)) { + break; + } + } while (--loops); + return loops ? 0 : -4; +} + +static int smbus_wait_until_ready(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1) == 0) { + break; + } + if (loops == (SMBUS_TIMEOUT / 2)) { + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + } + } while (--loops); + return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT; +} + +static int smbus_wait_until_done(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1) == 0) { + break; + } + } while (--loops); + return loops ? 0 : SMBUS_WAIT_UNTIL_DONE_TIMEOUT; +} +static int smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + if (smbus_wait_until_ready() < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + } + + /* setup transaction */ + /* disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* clear the data byte... */ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* start a byte read, with interrupts disabled */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + /* poll for it to start */ + if (smbus_wait_until_active() < 0) { + return -4; + } + + /* poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + /* Ignore the Host Busy & Command Complete ? */ + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) | (1 << 0)); + + /* read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + + if (global_status_register != 0) { + return SMBUS_ERROR; + } + return byte; +} Index: src/southbridge/via/vt82c686/Kconfig =================================================================== --- src/southbridge/via/vt82c686/Kconfig (revision 0) +++ src/southbridge/via/vt82c686/Kconfig (revision 0) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_VIA_VT82C686 + bool + select IOAPIC Index: src/southbridge/via/vt82c686/Makefile.inc =================================================================== --- src/southbridge/via/vt82c686/Makefile.inc (revision 0) +++ src/southbridge/via/vt82c686/Makefile.inc (revision 0) @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007, 2009 Rudolf Marek <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += vt82c686.o Index: src/southbridge/via/vt82c686/chip.h =================================================================== --- src/southbridge/via/vt82c686/chip.h (revision 5664) +++ src/southbridge/via/vt82c686/chip.h (working copy) @@ -18,18 +18,23 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_VIA_VT82C686 -#define _SUPERIO_VIA_VT82C686 +#ifndef SOUTHBRIDGE_VIA_VT82C686_CHIP_H +#define SOUTHBRIDGE_VIA_VT82C686_CHIP_H #include <device/device.h> -#include <pc80/keyboard.h> -#include <uart8250.h> +//#include <pc80/keyboard.h> +//#include <uart8250.h> -extern struct chip_operations superio_via_vt82c686_ops; +extern const struct chip_operations southbridge_via_vt82c686_ops; -struct superio_via_vt82c686_config { - struct uart8250 com1, com2; - struct pc_keyboard keyboard; +struct southbridge_via_vt82c686_config { + int enable_com_ports:1; + int enable_keyboard:1; + int enable_nvram:1; + int ide0_enable:1; + int ide1_enable:1; + int ide_legacy_enable:1; + int usb_enable:1; }; -#endif /* _SUPERIO_VIA_VT82C686 */ +#endif /* SOUTHBRIDGE_VIA_VT82C686_CHIP_H */ Index: src/southbridge/via/vt82c686/vt82c686.c =================================================================== --- src/southbridge/via/vt82c686/vt82c686.c (revision 0) +++ src/southbridge/via/vt82c686/vt82c686.c (revision 0) @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "vt82c686.h" + +static void vt82c686_enable(struct device *dev) +{ + /* TODO: Nothing to do? */ +} + +const struct chip_operations southbridge_via_vt82c686_ops = { + CHIP_NAME("VIA VT82C686 Southbridge") + .enable_dev = vt82c686_enable, +}; Index: src/Kconfig =================================================================== --- src/Kconfig (revision 5664) +++ src/Kconfig (working copy) @@ -510,6 +510,7 @@ || NORTHBRIDGE_AMD_AMDK8 \ || NORTHBRIDGE_VIA_CN700 \ || NORTHBRIDGE_VIA_CX700 \ + || NORTHBRIDGE_VIA_VT694 \ || NORTHBRIDGE_VIA_VX800 \ || NORTHBRIDGE_INTEL_E7501 \ || NORTHBRIDGE_INTEL_I440BX \ Index: src/mainboard/asus/Kconfig =================================================================== --- src/mainboard/asus/Kconfig (revision 5664) +++ src/mainboard/asus/Kconfig (working copy) @@ -30,6 +30,7 @@ source "src/mainboard/asus/p2b-f/Kconfig" source "src/mainboard/asus/p3b-f/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" +source "src/mainboard/asus/medion2001/Kconfig" source "src/mainboard/asus/mew-am/Kconfig" source "src/mainboard/asus/mew-vm/Kconfig" Index: src/mainboard/asus/medion2001/Kconfig =================================================================== --- src/mainboard/asus/medion2001/Kconfig (revision 0) +++ src/mainboard/asus/medion2001/Kconfig (revision 0) @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Anders Jenbo <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ASUS_MEDION2001 + bool "MEDION2001" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_VIA_VT694 + select SOUTHBRIDGE_VIA_VT82C686 + select ROMCC + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_256 + +config MAINBOARD_DIR + string + default asus/medion2001 + depends on BOARD_ASUS_MEDION2001 + +config MAINBOARD_PART_NUMBER + string + default "MED 2001" + depends on BOARD_ASUS_MEDION2001 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ASUS_MEDION2001 + +config IRQ_SLOT_COUNT + int + default 6 + depends on BOARD_ASUS_MEDION2001 + Index: src/mainboard/asus/medion2001/romstage.c =================================================================== --- src/mainboard/asus/medion2001/romstage.c (revision 0) +++ src/mainboard/asus/medion2001/romstage.c (revision 0) @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <console/console.h> +#include "lib/ramtest.c" +#include "southbridge/via/vt82c686/vt82c686_early_smbus.c" +#include "northbridge/via/vt694/raminit.h" +#include "lib/debug.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "southbridge/via/vt82c686/vt82c686_early_serial.c" + +//TODO 0x00 is temp as vt82c686_enable_serial() doesn't yet use this +#define SERIAL_DEV PNP_DEV(0x3f0, 0x00) + +#include "northbridge/via/vt694/raminit.c" + + +static void main(unsigned long bist) +{ + if (bist == 0) + early_mtrr_init(); + + vt82c686_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); +} + Index: src/mainboard/asus/medion2001/devicetree.cb =================================================================== --- src/mainboard/asus/medion2001/devicetree.cb (revision 0) +++ src/mainboard/asus/medion2001/devicetree.cb (revision 0) @@ -0,0 +1,48 @@ +chip northbridge/via/vt694 # Northbridge + device lapic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/via/vt82c686 # Southbridge + device pci 4.0 on + chip southbridge/via/vt82c686 + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.4 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 3f0.5 on # PS/2 mouse + irq 0x70 = 12 + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # USB + device pci 4.4 on end # ACPI + device pci 5.0 on end # Audio + end + end +end Index: src/mainboard/asus/medion2001/devicetree.cb.full =================================================================== --- src/mainboard/asus/medion2001/devicetree.cb.full (revision 0) +++ src/mainboard/asus/medion2001/devicetree.cb.full (revision 0) @@ -0,0 +1,48 @@ +chip northbridge/via/vt694 # Northbridge + device lapic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/via/vt82c686 # Southbridge + device pci 4.0 on + chip southbridge/via/vt82c686 + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.4 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 3f0.5 on # PS/2 mouse + irq 0x70 = 12 + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # USB + device pci 4.4 on end # ACPI + device pci 5.0 on end # Audio + end + end +end Index: src/mainboard/asus/medion2001/irq_tables.c =================================================================== --- src/mainboard/asus/medion2001/irq_tables.c (revision 0) +++ src/mainboard/asus/medion2001/irq_tables.c (revision 0) @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x586, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x27, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x04 << 3) | 0x0, {{0x05, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}}, 0x0, 0x0}, + {0x00, (0x0b << 3) | 0x0, {{0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x05, 0x1eb8}, {0x01, 0x1eb8}}, 0x1, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{0x03, 0x1eb8}, {0x05, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}}, 0x2, 0x0}, + {0x00, (0x09 << 3) | 0x0, {{0x05, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}}, 0x3, 0x0}, + {0x00, (0x05 << 3) | 0x0, {{0x05, 0x1eb8}, {0x00, 0x1eb8}, {0x00, 0x1eb8}, {0x00, 0x1eb8}}, 0x0, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x00, 0x1eb8}, {0x00, 0x1eb8}}, 0x4, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Index: src/mainboard/asus/medion2001/chip.h =================================================================== --- src/mainboard/asus/medion2001/chip.h (revision 0) +++ src/mainboard/asus/medion2001/chip.h (revision 0) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; Index: src/mainboard/asus/medion2001/mainboard.c =================================================================== --- src/mainboard/asus/medion2001/mainboard.c (revision 0) +++ src/mainboard/asus/medion2001/mainboard.c (revision 0) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS MEDION2001 Mainboard") +}; + Index: src/northbridge/via/Kconfig =================================================================== --- src/northbridge/via/Kconfig (revision 5664) +++ src/northbridge/via/Kconfig (working copy) @@ -1,6 +1,7 @@ source src/northbridge/via/cn700/Kconfig source src/northbridge/via/cx700/Kconfig source src/northbridge/via/cn400/Kconfig +source src/northbridge/via/vt694/Kconfig source src/northbridge/via/vt8601/Kconfig source src/northbridge/via/vt8623/Kconfig source src/northbridge/via/vx800/Kconfig Index: src/northbridge/via/Makefile.inc =================================================================== --- src/northbridge/via/Makefile.inc (revision 5664) +++ src/northbridge/via/Makefile.inc (working copy) @@ -1,3 +1,4 @@ +subdirs-$(CONFIG_NORTHBRIDGE_VIA_VT694) += vt694 subdirs-$(CONFIG_NORTHBRIDGE_VIA_VT8601) += vt8601 subdirs-$(CONFIG_NORTHBRIDGE_VIA_VT8623) += vt8623 subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700 Index: src/northbridge/via/vt694/Kconfig =================================================================== --- src/northbridge/via/vt694/Kconfig (revision 0) +++ src/northbridge/via/vt694/Kconfig (revision 0) @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Anders Jenbo <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config FALLBACK_SIZE + int + default 0 + depends on NORTHBRIDGE_VIA_VT694 + Index: src/northbridge/via/vt694/vt694.h =================================================================== --- src/northbridge/via/vt694/vt694.h (revision 0) +++ src/northbridge/via/vt694/vt694.h (revision 0) @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: + * - Name: VIA VT82C694X Apollo Pro133A + * - PDF: ds_694x_ApolloPro133A.pdf + */ + +/* + * Host-to-PCI Bridge Registers. + * The values in parenthesis are the default values as per datasheet. + * Any addresses between 0x00 and 0xff not listed below are Reserved + * and should not be touched. + */ + + +/* NBCR 0x50 - Configuration Registers + * [7] In-Order Queue Depth (IOQD) + * 1 = In-order queue = 4-level + * 0 = In-order queue = 1-level + * [6] Read-Around-Write + * 0 = Disable + * 1 = Enable + * [5] Reserved + * [4] Defer Retry When HLOCK Active + * 0 = Disable + * 1 = Enable + * [1-3] Reserved + * [0] CPU/PCI Master Read DRAM Timing + * 0 = Start DRAM read after snoop complete + * 1 = Start DRAM read befor snoop complete + */ +#define NBCR0 0x50 + +/* NBCR 0x51 - Configuration Registers + * [7] CPU Read DRAM 0ws for Back-to-Back Read Transactions + * 0 = Disable + * 1 = Enable + * [6] CPU Write DRAM 0ws for Back-to-Back Read Transactions + * 0 = Disable + * 1 = Enable + * [5] Reserved + * [4] Fast Response (HIT/HITM sample 1T erlier) + * 0 = Disable + * 1 = Enable + * [3] Non-Posted IOW + * 0 = Disable + * 1 = Enable + * [2] CE Silicon (Reserved): Zero Length Write + * 0 = Disable + * 1 = Enable - must be set to 1 + * [1] Reserved + * [0] Concurrent PCI Master / Host Operation + * 0 = Disable + * 1 = Enable + */ +#define NBCR1 0x51 + +/* NBCR 0x52 - Configuration Registers + * [7] GTL I/O Buffer Pullup + * 0 = Disable (if MAB6 Strap is 1) + * 1 = Enable (if MAB6 Strap is 0) + * [6] RAW Write Retire Policy (After 2 Writes) + * 0 = Disable + * 1 = Enable + * [5] Quick Start Selected + * 0 = Disable (if MAB10 Strap is 1) + * 1 = Enable (if MAB10 Strap is 0) + * [0-4] Snoop Stall Count + * 0x00 = Disable dynamic defer + * 0x01-0x1f (default is 0x10) + */ +#define NBCR2 0x52 + +/* NBCR 0x53 - Configuration Registers + * [7] HREQ + * 0 = Disable + * 1 = Enable + * [6] SDRAM Frequincy Higher Then CPU FSB Frequincy + * 0 = Disable + * 1 = Enable + * [5] PCI/AGP Master-to-CPU / CPU-to-AGP Slave Concurrency + * 0 = Disable + * 1 = Enable + * [4] HPRI Function + * 0 = Disable + * 1 = Enable + * [3] P6Lock Function + * 0 = Disable + * 1 = Enable + * [2] Line Write / Write Back Without Lmplicit Write Back Data + * 0 = Disable + * 1 = Enable + * [1] PCI Master Pipeline Access + * 0 = Disable + * 1 = Enable + * [0] Initialization of Fast Write Address Selection + * 1 = Head + * 0 = Tail + */ +#define NBCR3 0x53 + +/* NBCR 0x54 - Configuration Registers + * [7-6] Reserved (Do Not Programm) + * [3-5] Reserved + * [2] CE Silicon (Reserved): Zero Length Write + * 0 = Disable + * 1 = Enable - must be set to 1 + * [1] Invalid CPU Internal Cache on PCI Master Access + * 0 = Disable + * 1 = Enable + * [0] 1-1-1-1 PMRDY for PCI Master Access + * 0 = Disable + * 1 = Enable + */ +#define NBCR4 0x54 + +/* DRAMC - DRAM type + * 0x60 + * + * 00 FPG + * 01 EDO + * 10 Reserved + * 11 SDRAM + * + * [7:6] Bank 6/7 type + * [5:4] Bank 4/5 type + * [3:2] Bank 2/3 type + * [1:0] Bank 1/0 type + */ +#define DRAMTY 0x60 + + +/* DRB[0:7] - DRAM Row Boundary Registers + * 0x60 - 0x67 + * + * An array of 8 byte registers, which hold the ending memory address + * assigned to each bank, in 8MB granularity. + * + * 0x5a DRB0 = Total memory in row0 (in 8 MB) + * 0x5b DRB1 = Total memory in row0+1 (in 8 MB) + * 0x5c DRB2 = Total memory in row0+1+2 (in 8 MB) + * 0x5d DRB3 = Total memory in row0+1+2+3 (in 8 MB) + * 0x5e DRB4 = Total memory in row0+1+2+3+4 (in 8 MB) + * 0x5f DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB) + * 0x56 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB) + * 0x57 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB) + */ +#define DRB0 0x5a +#define DRB1 0x5b +#define DRB2 0x5c +#define DRB3 0x5d +#define DRB4 0x5e +#define DRB5 0x5f +#define DRB6 0x56 +#define DRB7 0x57 + + +/* SDRAM Timing for all banks + * no interleave + * Standard DIMM type + * ras precharge 3T, RAS pulse 3T + * cas2 is 0xd6, cas3 is 0xe6 + */ +#define DRAMT0 0x64 +#define DRAMT1 0x65 +#define DRAMT2 0x66 +#define DRAMT3 0x67 + + +#define DRAMC 0x68 /* DRAM Control. */ +#define DRAMCL 0x69 /* DRAM Clock. */ +#define RC 0x6a /* Refresh counter. */ +#define DRAMD 0x6d /* DRAM Drive Strength. */ +#define DRAMECC 0x6e /* DRAM ECC. */ +#define FDHC 0x63 /* Fixed SDRAM Hole Control. */ Index: src/northbridge/via/vt694/raminit.c =================================================================== --- src/northbridge/via/vt694/raminit.c (revision 0) +++ src/northbridge/via/vt694/raminit.c (revision 0) @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <spd.h> +#include <delay.h> +#include <stdlib.h> +#include "vt694.h" +#include "raminit.h" + +/*----------------------------------------------------------------------------- +Macros and definitions. +-----------------------------------------------------------------------------*/ + +/* Debugging macros. */ +#if CONFIG_DEBUG_RAM_SETUP +#define PRINT_DEBUG(x) print_debug(x) +#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) +#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) +#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) + + +#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) +#else +#define PRINT_DEBUG(x) +#define PRINT_DEBUG_HEX8(x) +#define PRINT_DEBUG_HEX16(x) +#define PRINT_DEBUG_HEX32(x) +#define DUMPNORTH() +#endif + +#define NB PCI_DEV(0, 0, 0) + +/* SDRAMC[2-0] - SDRAM Mode Select (SMS). Device 0 Offset 6C - SDRAM Control (00h) RW */ +#define RAM_COMMAND_NORMAL 0x0 +#define RAM_COMMAND_NOP 0x1 +#define RAM_COMMAND_PRECHARGE 0x2 +#define RAM_COMMAND_MRS 0x3 +#define RAM_COMMAND_CBR 0x4 + +/* +Device 0 Offset 6A - Refresh Counter (00h) ...................RW + 7-0 Refresh Counter (in units of 16 MCLKs) + 00 DRAM Refresh Disabled.......................default + 01 32 MCLKs + 02 48 MCLKs + 03 64 MCLKs + 04 80 MCLKs + 05 96 MCLKs*/ + +static void sdram_set_registers(void) +{ + device_t north = (device_t) PCI_DEV(0, 0, 0); + + PRINT_DEBUG("Northbridge prior to SDRAM init:\n"); + DUMPNORTH(); + + /* Set default NB options. */ + //1111 1110 + //1010 1100 + pci_write_config8(north, NBCR0, 0xac); + //1101 1111 + //0000 0100 + pci_write_config8(north, NBCR1, 0x04); + //1100 1000 + //0010 0000 + pci_write_config8(north, NBCR2, 0x20); + //1001 1000 + //0000 0001 + pci_write_config8(north, NBCR3, 0x01); + //0000 0100 + pci_write_config8(north, NBCR4, 0x04); + + /* Choose SDRAM. */ + pci_write_config8(north, DRAMTY, 0xFF); + + /* Set the DRBs to zero for now, this will be fixed later. */ + pci_write_config8(north, DRB0, 0x00); + pci_write_config8(north, DRB1, 0x00); + pci_write_config8(north, DRB2, 0x00); + pci_write_config8(north, DRB3, 0x00); + pci_write_config8(north, DRB4, 0x00); + pci_write_config8(north, DRB5, 0x00); + pci_write_config8(north, DRB6, 0x00); + pci_write_config8(north, DRB7, 0x00); + + /* No, CMD 3T, Standard, CAS 3T, TRAS 6T, TRP 3T */ + pci_write_config8(north, DRAMT0, 0xe4); + pci_write_config8(north, DRAMT1, 0xe4); + pci_write_config8(north, DRAMT2, 0xe4); + pci_write_config8(north, DRAMT3, 0xe4); + + + /* Dram frequency select. + * enable 4K pages for 64M dram. + * Set to match FSB + */ + pci_write_config8(north, DRAMCL, 0x3c); + + /* Refresh counter + * Reset it + */ + pci_write_config8(north, RC, 0x00); + + /* DRAM read latch delay of 1.5 ns, MD drive 8 mA, + * high drive strength + */ + pci_write_config8(north, DRAMD, 0x7f); +} + +static void sdram_set_spd_registers(void) +{ + PRINT_DEBUG("sdram_set_spd_registers:\n"); +} + +static void sdram_enable(void) +{ + PRINT_DEBUG("sdram_enable:\n"); + int i; + + /* 0. Wait until power/voltages and clocks are stable (200us). */ + udelay(200); + + /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ + PRINT_DEBUG("RAM Enable 1: Apply NOP\n"); + udelay(200); + + /* 2. Precharge all. Wait tRP. */ + PRINT_DEBUG("RAM Enable 2: Precharge all\n"); + udelay(1); + + /* 3. Perform 8 refresh cycles. Wait tRC each time. */ + PRINT_DEBUG("RAM Enable 3: CBR\n"); + for (i = 0; i < 8; i++) { + udelay(1); + } + + /* 4. Mode register set. Wait two memory cycles. */ + PRINT_DEBUG("RAM Enable 4: Mode register set\n"); + udelay(2); + + + /* 6. Finally enable refresh. */ + PRINT_DEBUG("RAM Enable 6: Enable refresh\n"); + udelay(1); + + PRINT_DEBUG("Northbridge following SDRAM init:\n"); + DUMPNORTH(); +} Index: src/northbridge/via/vt694/Makefile.inc =================================================================== --- src/northbridge/via/vt694/Makefile.inc (revision 0) +++ src/northbridge/via/vt694/Makefile.inc (revision 0) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Anders Jenbo <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += northbridge.o + Index: src/northbridge/via/vt694/northbridge.c =================================================================== --- src/northbridge/via/vt694/northbridge.c (revision 0) +++ src/northbridge/via/vt694/northbridge.c (revision 0) @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <cpu/cpu.h> +#include <pc80/keyboard.h> +#include "chip.h" +#include "northbridge.h" + + +static void northbridge_init(device_t dev) +{ + printk(BIOS_SPEW, "Northbridge Init\n"); +} + +static struct device_operations northbridge_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x0601, /* 0x8601 is the AGP bridge? */ +}; + +static void ram_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + best = *best_p; + if (!best || (best->base > new->base)) { + best = new; + } + *best_p = best; +} + +static uint32_t find_pci_tolm(struct bus *bus) +{ + struct resource *min; + uint32_t tolm; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + tolm = 0xffffffffUL; + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + +static void pci_domain_set_resources(device_t dev) +{ + device_t mc_dev; + uint32_t pci_tolm; + + pci_tolm = find_pci_tolm(&dev->link[0]); + mc_dev = dev->link[0].children; + if (mc_dev) { + unsigned long tomk, tolmk; + int idx; + + /* Figure out which areas are/should be occupied by RAM. The + * value of the highest DRB denotes the end of the physical + * memory (in units of 8MB). + */ + tomk = ((unsigned long)pci_read_config8(mc_dev, 0x00)); + + /* Convert to KB. */ + tomk *= (8 * 1024); + + printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024); + + /* Compute the top of low memory. */ + tolmk = pci_tolm >> 10; + + if (tolmk >= tomk) { + /* The PCI hole does not overlap the memory. */ + tolmk = tomk; + } + + /* Report the memory regions. */ + idx = 10; + ram_resource(dev, idx++, 0, tolmk); + +#if CONFIG_WRITE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; +#endif + } + assign_resources(&dev->link[0]); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(&dev->link[0]); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_via_vt694_ops = { + CHIP_NAME("VIA VT694 Northbridge") + .enable_dev = enable_dev, +}; Index: src/northbridge/via/vt694/raminit.h =================================================================== --- src/northbridge/via/vt694/raminit.h (revision 0) +++ src/northbridge/via/vt694/raminit.h (revision 0) @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef RAMINIT_H +#define RAMINIT_H + +//TODO Figure out the if it support 4 or 3, VIA says max 512 per sim and max 1.5G total. +//Atleast one ASUS board using VIA Apollo Pro 133A has 4 DIMMs +/* The VT694 supports up to three, or maybe 4... DIMMs. */ +#define DIMM_SOCKETS 3 + +//TODO are theas numbers right? +/* DIMMs 1-4 are at 0x56, 0x57, 0x5a, 0x5f. */ +#define DIMM_SPD_BASE 0x5a + +#endif /* RAMINIT_H */ Index: src/northbridge/via/vt694/chip.h =================================================================== --- src/northbridge/via/vt694/chip.h (revision 0) +++ src/northbridge/via/vt694/chip.h (revision 0) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_via_vt694_config +{ +}; + +extern struct chip_operations northbridge_via_vt694_ops; Index: src/northbridge/via/vt694/northbridge.h =================================================================== --- src/northbridge/via/vt694/northbridge.h (revision 0) +++ src/northbridge/via/vt694/northbridge.h (revision 0) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_VIA_VT694_H +#define NORTHBRIDGE_VIA_VT694_H + +extern unsigned int vt694_scan_root_bus(device_t root, unsigned int max); + +#endif /* NORTHBRIDGE_VIA_VT694_H */
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