Author: oxygene Date: Wed Sep 8 13:00:25 2010 New Revision: 5788 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5788
Log: Code must not access the smbus registers before the RTC power well is ready (PSON gating). Some boards boot faster than this power well stabilization, and thus see bad data when accessing the smbus registers. Signed-off-by: Kevin O'Connor <[email protected]> Acked-by: Peter Stuge <[email protected]> Modified: trunk/src/southbridge/via/vt8237r/vt8237r.h trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Modified: trunk/src/southbridge/via/vt8237r/vt8237r.h ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r.h Wed Sep 8 12:58:02 2010 (r5787) +++ trunk/src/southbridge/via/vt8237r/vt8237r.h Wed Sep 8 13:00:25 2010 (r5788) @@ -47,6 +47,7 @@ #define IDE_UDMA 0x50 /* SMBus */ +#define VT8237R_PSON 0x82 #define VT8237R_POWER_WELL 0x94 #define VT8237R_SMBUS_IO_BASE_REG 0xd0 #define VT8237R_SMBUS_HOST_CONF 0xd2 Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Wed Sep 8 12:58:02 2010 (r5787) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Wed Sep 8 13:00:25 2010 (r5788) @@ -132,12 +132,15 @@ return val; } +#define PSONREADY_TIMEOUT 0x7fffffff + /** * Enable the SMBus on VT8237R-based systems. */ void enable_smbus(void) { device_t dev; + int loops; /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, @@ -150,6 +153,12 @@ die("Power management controller not found\n"); } + /* Make sure the RTC power well is up before touching smbus. */ + loops = 0; + while (!(pci_read_config8(dev, VT8237R_PSON) & (1<<6)) + && loops < PSONREADY_TIMEOUT) + ++loops; + /* * 7 = SMBus Clock from RTC 32.768KHz * 5 = Internal PLL reset from susp -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
