Am 08.09.2010 12:55, schrieb Mats Erik Andersson: > with pci-id 1002:4742. Thus I do arrive at a serial console, as well as > the usual text console. This is a good thing, if not for other reasons > that I managed to amalgamate CBFS/VGA-BIOS/SeaBIOS! I guess you meant "coreboot"? CBFS is just the filesystem.
> When booting Debian GNU/Linux via Coreboot/SeaBIOS, the kernel complains > > [0.204012] weird, boot CPU(#0) not listed by BIOS. Some of the tables (mptable and the like) are probably incomplete or missing. The completeness of tables and ACPI varies a lot between boards. We work on unifying the code, to improve matters for existing boards and simplify support for new ones, but it's far from completed. > "WARNING - Timeout at await_ide:39!". Might be incomplete IDE init. coreboot usually (depends on chipset) does no init at all. Some chipset docs actually require some (eg. figure out if 80-pin cables are used, and set a bit if so) > The uhci_hcd circuitry is detected, but it is not assigned an IRQ, > so Linux as well as OpenBSD considers it to be broken. SeaBIOS > reports an io-port 0x20c0, though. IO Ports are assigned properly in generic code, but assigning IRQ is mainboard/chipset specific code. > Neither Linux, nor OpenBSD, are able to accomplish a complete power down, > as power supply is still applied after shutdown. The board has no ACPI support at all (and we don't do APM either). That might be the reason why this isn't working. > Moving the single DIMM to another socket, makes the nortbridge > initialisation fail immediately after printing > > "Northbridge following SDRAM init". Again, chipset specific code. Regards, Patrick -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
