Arne Georg Gleditsch <[email protected]> writes:
> I can confirm that this removes the earlier observed delays for me.
> Obviously, this is AMD-specific code that needs to be hooked in in a
> proper manner, but this definately seems to be the culprit.
Apparently, it's not crucial to clear this at the exact moment we switch
to using ram, so something like the appended is perhaps more
appropriate. Confirmed to work on hw.
Signed-off-by: Arne Georg Gleditsch <[email protected]>
--
Arne.
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 992c957..6f61fc3 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -113,6 +113,11 @@ static void model_10xxx_init(device_t dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
+ /* Clear ClLinesToNbDis */
+ msr = rdmsr(BU_CFG2_MSR);
+ msr.lo &= ~(1 << 15);
+ wrmsr(BU_CFG2_MSR, msr);
+
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 3693891..400071d 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3189,7 +3189,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
print_t("\tmct_FinalMCT_D: Clr Cl, Wb\n");
- mct_ClrClToNB_D(pMCTstat, pDCTstat);
+ /* ClrClToNB_D postponed til we're done executing from ROM */
mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
}
--
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