"Scott Duplichan" <[email protected]> writes:
> I think it would be best to clear bit 35 of msr c001_102a in the AP
> cores as well as the BSP core. Otherwise, the OS might see AP cores
> having slightly lower performance than the BSP core. This bit affects
> family 10h revC and newer (45 nm).
Ok, so here's a patch adding this. Clearing bit 35 is done
unconditionally for all fam10 cpus, is that ok? Setting is done based
on processor type in defaults.h, as before.
Signed-off-by: Arne Georg Gleditsch <[email protected]>
--
Arne.
diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 2fbfbb2..9a0e349 100644
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -91,7 +91,7 @@ static const struct {
{ BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL,
0x00000000, 1 << (35-32),
- 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram() ) */
+ 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */
};
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 6f61fc3..a0e1f6f 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -113,9 +113,11 @@ static void model_10xxx_init(device_t dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
- /* Clear ClLinesToNbDis */
msr = rdmsr(BU_CFG2_MSR);
+ /* Clear ClLinesToNbDis */
msr.lo &= ~(1 << 15);
+ /* Clear bit 35 as per Erratum 343 */
+ msr.hi &= ~(1 << (35-32));
wrmsr(BU_CFG2_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
--
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