Author: mjones Date: Tue Sep 14 19:28:41 2010 New Revision: 5814 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5814
Log: This patch corrects a coding error in the original implementation of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code sets msr c001_102a bit 3 when bit 35 was intended. Signed-off-by: Scott Duplichan <[email protected]> Acked-by: Marc Jones <[email protected]> Modified: trunk/src/cpu/amd/car/cache_as_ram.inc Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Mon Sep 13 21:31:21 2010 (r5813) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Tue Sep 14 19:28:41 2010 (r5814) @@ -129,8 +129,8 @@ /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ rdmsr - /* Set bit 35 to 1 in EAX */ - bts $35, %eax + /* Set bit 35 to 1 in EAX:EDX */ + bts $35-32, %edx /* write back the modified register EDX:EAX to the MSR specified in ECX */ wrmsr -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
