Author: mjones Date: Fri Sep 17 02:13:52 2010 New Revision: 5817 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5817
Log: Clear bit 35 of msr c001_102a in Fam10 rev C cores. Signed-off-by: Arne Georg Gleditsch <[email protected]> Acked-by: Scott Duplichan <[email protected]> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Thu Sep 16 23:36:44 2010 (r5816) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Fri Sep 17 02:13:52 2010 (r5817) @@ -91,7 +91,7 @@ { BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL, 0x00000000, 1 << (35-32), - 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram() ) */ + 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */ }; Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Thu Sep 16 23:36:44 2010 (r5816) +++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Fri Sep 17 02:13:52 2010 (r5817) @@ -113,9 +113,11 @@ msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - /* Clear ClLinesToNbDis */ msr = rdmsr(BU_CFG2_MSR); + /* Clear ClLinesToNbDis */ msr.lo &= ~(1 << 15); + /* Clear bit 35 as per Erratum 343 */ + msr.hi &= ~(1 << (35-32)); wrmsr(BU_CFG2_MSR, msr); /* Write protect SMM space with SMMLOCK. */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
