Now here are my results with the patched Memtest86+ version 4.1. Check the attached files.
As you can see it is far way better, even if it is not working, at least i can see that the memory is recognized correctly, wich is pretty good. Memtest86+ is still crashing on test starting (after 3%), but really not important so far, as long as my computer does not crash in normal operation mode. Another question, what may the consequences be not supporting e820 in bios, for other OS like windows for example ? Does another OS use this feature e820 ? Cheers Frédéric ________________________________________ De : [email protected] [[email protected]] de la part de STEMMELIN, FREDERIC (FREDERIC)** CTR ** [[email protected]] Date d'envoi : dimanche 19 septembre 2010 15:35 À : Juhana Helovuo Cc : [email protected] Objet : [coreboot] RE : [PATCH] Re: RE : RE : First coreboot build for Tyan s2895 K8WE mobo with seabios payload, computer starts, but graphical ubuntu 64bits is crashing Thank you very much for your help, in the mean time i have very goods news, yes my Tyan s2895 is BOOTING now :) I found what was the origin of teh crashes after i was trying to boot a debian livecd with "noapic noapm" and such other things as kernel parameters (i didnt change the defaut settings). I saw a kerneloops on screen after kernel was trying to set a IRQ for the intel network card, with error -39 (or -38 i dont remember exactly). Now after remowing my Intel PRO1000MT server network card from PCI-X slot 6, i can boot without any problems :) Memtest86+ v 4.0 is still not working, but less important now that i am sure my problem was not RAM related :) I will anyway try your instructions with patchs and report back. By the way, i was not able to compile following with coreboot v4: - corinfo => compile errors - tint => same - memtest as payload => same I tried several things like changing Makefile, but it didnt work as i dont understand what it doest exactly. Thank's for your support. PS: If needed i can provide all informations what mayy necessary to find the PCI-X bug with teh network card, if you wish. ________________________________________ De : Juhana Helovuo [[email protected]] Date d'envoi : samedi 18 septembre 2010 18:23 À : STEMMELIN, FREDERIC (FREDERIC)** CTR ** Cc : [email protected] Objet : [PATCH] Re: [coreboot] RE : RE : First coreboot build for Tyan s2895 K8WE mobo with seabios payload, computer starts, but graphical ubuntu 64bits is crashing On Sat, 2010-09-18 at 00:14 +0200, STEMMELIN, FREDERIC (FREDERIC)** CTR ** wrote: > In the mean time i checked RAM with memtest86+ v4.0 provided with > Ubuntu 10.04, and it is not working at all, 0kb RAM detected with > coreboot+seabios. > On tyan bios all the RAM is detected properly (no errors on tests > too). > > I have 4*2GB ECC RAM from crucial, dont remember ref, can probably find it > somewhere. Hello, My guess from your memtest86+ printouts is the following: With Tyan BIOS, memtest86+ uses BIOS call "e820" to find out the available RAM. With Coreboot + SeaBIOS, memtes86+ detects that there are Coreboot tables in memory ("LxBIOS"), but for some reason thinks that the table reports 0k memory. This may be because your memtest86+ version does not support Coreboot "high tables", and therefore detects the presence of Coreboot, but cannot read the contents of the table. Coreboot does not implement the e820 interface, but SeaBIOS should have it available. However, when memtest86+ detects that Coreboot is present, it ignores the e820 interface and tries to read the Coreboot tables. I have made a patch for memtest86+ v4.10, which adds better support for Coreboot and also multiboot tables. The patch is not my original work, but a combination of two patches, so the credit belongs to the original authors. Application instructions: * Download memtest86+ v 4.10 sources .tar.gz and untar * Apply patch, e.g. patch -p1 < ../coreboot-v4-and-multiboot-support-for-memtest86+-4.10.patch * Manually rename two files: % mv linuxbios.c coreboot.c % mv linuxbios_tables.h coreboot_tables.h * Build memtest86+ using "make" The build process creates two versions of the memtest86+ binary. "memtest" is multiboot-compatible ELF executable and "memtest.bin" is bootable image like a Linux kernel image. Choosing between these two depends on your boot method: BIOS, Coreboot only, Coreboot+SeaBIOS, or a bootloader. My success with memtest86+ has been rather limited, but maybe this works for you. Best regards, Juhana Helovuo -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
Memtest86+ v4.00 | Pass 0% AMD Opteron (0.09) 3014 MHz | Test 25% ######### L1 Cache: 64K 23546 MB/s | Test #1 [Address test, own address] L2 Cache: 1024K 5886 MB/s | Testing: 2048M - 3327M 8191M L3 Cache: None | Pattern: Memory : 8191M 2375 MB/s |------------------------------------------------- Chipset : AMD K8 IMC (ECC : Detect / Correct - Chipkill : On) Settings: RAM : 200 MHz (DDR401) / CAS : 3-3-3-8 / DDR1 (128 bits) WallTime Cached RsvdMem MemMap Cache ECC Test Pass Errors ECC Errs --------- ------ ------- -------- ----- --- ---- ---- ------ -------- 0:00:02 8191M 444K e820 on off Std 0 0 ----------------------------------------------------------------------------- (ESC)Reboot (c)configuration (SP)scroll_lock (CR)scroll_unlock
Memtest86+ v4.10 | Pass 0% AMD Opteron (0.09) 3015 MHz | Test 3% # L1 Cache: 64K 23558 MB/s | Test #0 [Address test, walking ones] L2 Cache: 1024K 6335 MB/s | Testing: 4096M - 6144M 8192M L3 Cache: None | Pattern: 00000000 Memory : 8192M 2301 MB/s |------------------------------------------------- Chipset : AMD K8 IMC (ECC : Detect / Correct - Chipkill : On) Settings: RAM : 201 MHz (DDR402) / CAS : 3-3-3-8 / DDR1 (128 bits) WallTime Cached RsvdMem MemMap Cache ECC Test Pass Errors ECC Errs --------- ------ ------- -------- ----- --- ---- ---- ------ -------- 0:00:00 8192M 0K corebt on off Std 0 0 ----------------------------------------------------------------------------- (ESC)Reboot (c)configuration (SP)scroll_lock (CR)scroll_unlock
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
