See patch. I also cleaned up the Debug Port page in the wiki a bit.
http://www.coreboot.org/EHCI_Debug_Port For now I marked all chipsets where we have Debug Port code as untested, I have a feeling the functionality was rarely tested recently (or at all) so we should only mark those chipsets as tested where we actually have recent test reports. I'm not sure about the SiS966 Debug Port code, it looks copy-pasted from MCP55 to me, not sure if the functionality actually exists on that chipset and if the code is correct for that. Maybe someone with a SiS966 board could test this? I'll be able to test on two more chipsets (MCP55, ICH7) and mark them as tested in the wiki then, will report back. Can somebody test SB700? I guess it works fine as the SB600 does too, but a test report would be nice. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org
Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure. Without a (currently) dummy set_debug_port() function the build fails, this may or may not be fixed differently in the future. Manually build-tested on all SB600/SB700 boards, and tested on hardware on one SB600 board I own, works fine. Signed-off-by: Uwe Hermann <[email protected]> Index: src/southbridge/amd/sb600/sb600_enable_usbdebug.c =================================================================== --- src/southbridge/amd/sb600/sb600_enable_usbdebug.c (Revision 5830) +++ src/southbridge/amd/sb600/sb600_enable_usbdebug.c (Arbeitskopie) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <usbdebug.h> + #ifndef SB600_DEVN_BASE #define SB600_DEVN_BASE 0 @@ -27,6 +29,11 @@ #define EHCI_BAR 0xFEF00000 #define EHCI_DEBUG_OFFSET 0xE0 +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ +} + static void sb600_enable_usbdebug(u32 port) { set_debug_port(port); Index: src/southbridge/amd/sb700/sb700_enable_usbdebug.c =================================================================== --- src/southbridge/amd/sb700/sb700_enable_usbdebug.c (Revision 5830) +++ src/southbridge/amd/sb700/sb700_enable_usbdebug.c (Arbeitskopie) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <usbdebug.h> + #ifndef SB700_DEVN_BASE #define SB700_DEVN_BASE 0 @@ -27,6 +29,11 @@ #define EHCI_BAR 0xFEF00000 #define EHCI_DEBUG_OFFSET 0xE0 +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ +} + static void sb700_enable_usbdebug(u32 port) { set_debug_port(port); Index: src/mainboard/asrock/939a785gmh/romstage.c =================================================================== --- src/mainboard/asrock/939a785gmh/romstage.c (Revision 5830) +++ src/mainboard/asrock/939a785gmh/romstage.c (Arbeitskopie) @@ -53,6 +53,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -176,6 +181,12 @@ sio_init(); w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/kontron/kt690/romstage.c =================================================================== --- src/mainboard/kontron/kt690/romstage.c (Revision 5830) +++ src/mainboard/kontron/kt690/romstage.c (Arbeitskopie) @@ -54,6 +54,11 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -125,6 +130,12 @@ dev=PNP_DEV(0x2e, W83627DHG_SP1); w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/gigabyte/ma78gm/romstage.c =================================================================== --- src/mainboard/gigabyte/ma78gm/romstage.c (Revision 5830) +++ src/mainboard/gigabyte/ma78gm/romstage.c (Arbeitskopie) @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -139,6 +145,12 @@ it8718f_disable_reboot(); uart_init(); console_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + printk(BIOS_DEBUG, "\n"); Index: src/mainboard/gigabyte/ma785gmt/romstage.c =================================================================== --- src/mainboard/gigabyte/ma785gmt/romstage.c (Revision 5830) +++ src/mainboard/gigabyte/ma785gmt/romstage.c (Arbeitskopie) @@ -56,6 +56,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -135,6 +141,12 @@ it8718f_disable_reboot(); uart_init(); console_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/amd/mahogany/romstage.c =================================================================== --- src/mainboard/amd/mahogany/romstage.c (Revision 5830) +++ src/mainboard/amd/mahogany/romstage.c (Arbeitskopie) @@ -52,6 +52,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8718f/it8718f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -122,6 +127,12 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/amd/pistachio/romstage.c =================================================================== --- src/mainboard/amd/pistachio/romstage.c (Revision 5830) +++ src/mainboard/amd/pistachio/romstage.c (Arbeitskopie) @@ -46,6 +46,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -117,8 +122,14 @@ sb600_lpc_init(); /* Pistachio used a FPGA to enable serial debug instead of a SIO - * and it doens't require any special setup. */ + * and it doesn't require any special setup. */ uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); post_code(0x03); Index: src/mainboard/amd/dbm690t/romstage.c =================================================================== --- src/mainboard/amd/dbm690t/romstage.c (Revision 5830) +++ src/mainboard/amd/dbm690t/romstage.c (Arbeitskopie) @@ -52,6 +52,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -123,6 +128,12 @@ /* it8712f_enable_serial does not use its 1st parameter. */ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/amd/mahogany_fam10/romstage.c =================================================================== --- src/mainboard/amd/mahogany_fam10/romstage.c (Revision 5830) +++ src/mainboard/amd/mahogany_fam10/romstage.c (Arbeitskopie) @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -138,6 +144,12 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); Index: src/mainboard/amd/tilapia_fam10/romstage.c =================================================================== --- src/mainboard/amd/tilapia_fam10/romstage.c (Revision 5830) +++ src/mainboard/amd/tilapia_fam10/romstage.c (Arbeitskopie) @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -138,6 +144,12 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); Index: src/mainboard/iei/kino-780am2-fam10/romstage.c =================================================================== --- src/mainboard/iei/kino-780am2-fam10/romstage.c (Revision 5830) +++ src/mainboard/iei/kino-780am2-fam10/romstage.c (Arbeitskopie) @@ -63,6 +63,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/fintek/f71859/f71859_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -142,6 +148,12 @@ f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/jetway/pa78vm5/romstage.c =================================================================== --- src/mainboard/jetway/pa78vm5/romstage.c (Revision 5830) +++ src/mainboard/jetway/pa78vm5/romstage.c (Arbeitskopie) @@ -67,6 +67,11 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -147,6 +152,12 @@ f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); Index: src/mainboard/technexion/tim8690/romstage.c =================================================================== --- src/mainboard/technexion/tim8690/romstage.c (Revision 5830) +++ src/mainboard/technexion/tim8690/romstage.c (Arbeitskopie) @@ -53,6 +53,11 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -124,6 +129,12 @@ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/technexion/tim5690/romstage.c =================================================================== --- src/mainboard/technexion/tim5690/romstage.c (Revision 5830) +++ src/mainboard/technexion/tim5690/romstage.c (Arbeitskopie) @@ -53,6 +53,11 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -130,6 +135,12 @@ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Index: src/mainboard/asus/m4a785-m/romstage.c =================================================================== --- src/mainboard/asus/m4a785-m/romstage.c (Revision 5830) +++ src/mainboard/asus/m4a785-m/romstage.c (Arbeitskopie) @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8712f/it8712f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -140,6 +146,12 @@ it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */ uart_init(); console_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
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