Author: uwe Date: Sun Sep 26 18:01:08 2010 New Revision: 5857 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5857
Log: Duplicate the MCP55 EHCI Debug Port enable code for use with CK804. Signed-off-by: Jonathan Kollasch <[email protected]> Acked-by: Uwe Hermann <[email protected]> Added: trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c - copied, changed from r5856, trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Modified: trunk/src/southbridge/nvidia/ck804/Kconfig Modified: trunk/src/southbridge/nvidia/ck804/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Kconfig Sun Sep 26 17:23:28 2010 (r5856) +++ trunk/src/southbridge/nvidia/ck804/Kconfig Sun Sep 26 18:01:08 2010 (r5857) @@ -1,6 +1,7 @@ config SOUTHBRIDGE_NVIDIA_CK804 bool select HAVE_HARD_RESET + select HAVE_USBDEBUG select IOAPIC config ID_SECTION_OFFSET Copied and modified: trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c (from r5856, trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c) ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Sun Sep 26 17:23:28 2010 (r5856, copy source) +++ trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c Sun Sep 26 18:01:08 2010 (r5857) @@ -26,9 +26,9 @@ #include <device/pci_def.h> #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif #define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ @@ -38,7 +38,7 @@ void set_debug_port(unsigned int port) { u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ + device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -47,9 +47,9 @@ pci_write_config32(dev, 0x74, dword); } -static void mcp55_enable_usbdebug(unsigned int port) +static void ck804_enable_usbdebug(unsigned int port) { - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ + device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ /* Mark the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
