Author: stepan Date: Mon Sep 27 23:11:54 2010 New Revision: 5868 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5868
Log: This patch moves one of the CAR configs to the socket from the single mainboard that uses it. Signed-off-by: Warren Turkal <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/cpu/intel/socket_441/Kconfig trunk/src/mainboard/intel/d945gclf/Kconfig Modified: trunk/src/cpu/intel/socket_441/Kconfig ============================================================================== --- trunk/src/cpu/intel/socket_441/Kconfig Mon Sep 27 23:08:40 2010 (r5867) +++ trunk/src/cpu/intel/socket_441/Kconfig Mon Sep 27 23:11:54 2010 (r5868) @@ -1,5 +1,21 @@ config CPU_INTEL_SOCKET_441 bool + +if CPU_INTEL_SOCKET_441 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_106CX select MMX select SSE + select CACHE_AS_RAM + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_INTEL_SOCKET_441 Modified: trunk/src/mainboard/intel/d945gclf/Kconfig ============================================================================== --- trunk/src/mainboard/intel/d945gclf/Kconfig Mon Sep 27 23:08:40 2010 (r5867) +++ trunk/src/mainboard/intel/d945gclf/Kconfig Mon Sep 27 23:11:54 2010 (r5868) @@ -38,7 +38,6 @@ select HAVE_ACPI_TABLES select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_512 - select CACHE_AS_RAM select GFXUMA select TINY_BOOTBLOCK @@ -46,14 +45,6 @@ string default intel/d945gclf -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "D945GCLF" -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
