Author: stepan Date: Mon Sep 27 23:18:26 2010 New Revision: 5871 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5871
Log: All these boards already had the CACHE_AS_RAM option in their individual configs. I just moved it the the CPU that they all use. Signed-off-by: Warren Turkal <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/cpu/amd/model_lx/Kconfig trunk/src/mainboard/amd/db800/Kconfig trunk/src/mainboard/amd/norwich/Kconfig trunk/src/mainboard/artecgroup/dbe61/Kconfig trunk/src/mainboard/digitallogic/msm800sev/Kconfig trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig trunk/src/mainboard/lippert/hurricane-lx/Kconfig trunk/src/mainboard/lippert/literunner-lx/Kconfig trunk/src/mainboard/lippert/roadrunner-lx/Kconfig trunk/src/mainboard/lippert/spacerunner-lx/Kconfig trunk/src/mainboard/pcengines/alix1c/Kconfig trunk/src/mainboard/pcengines/alix2d/Kconfig trunk/src/mainboard/traverse/geos/Kconfig trunk/src/mainboard/winent/pl6064/Kconfig Modified: trunk/src/cpu/amd/model_lx/Kconfig ============================================================================== --- trunk/src/cpu/amd/model_lx/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/cpu/amd/model_lx/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -1,25 +1,27 @@ config CPU_AMD_LX bool +if CPU_AMD_LX + +config CPU_SPECIFIC_OPTIONS + def_bool y + select CACHE_AS_RAM + config DCACHE_RAM_BASE hex default 0xc8000 - depends on CPU_AMD_LX config DCACHE_RAM_SIZE hex default 0x8000 - depends on CPU_AMD_LX config GEODE_VSA bool default y - depends on CPU_AMD_LX select PCI_OPTION_ROM_RUN_REALMODE config GEODE_VSA_FILE bool "Add a VSA image" - depends on CPU_AMD_LX help Select this option if you have an AMD Geode LX vsa that you would like to add to your ROM. @@ -29,9 +31,9 @@ config VSA_FILENAME string "AMD Geode LX VSA path and filename" - depends on GEODE_VSA_FILE && CPU_AMD_LX + depends on GEODE_VSA_FILE default "gpl_vsa_lx_102.bin" help The path and filename of the file to use as VSA. - +endif # CPU_AMD_LX Modified: trunk/src/mainboard/amd/db800/Kconfig ============================================================================== --- trunk/src/mainboard/amd/db800/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/amd/db800/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -10,7 +10,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR Modified: trunk/src/mainboard/amd/norwich/Kconfig ============================================================================== --- trunk/src/mainboard/amd/norwich/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/amd/norwich/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -9,7 +9,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR Modified: trunk/src/mainboard/artecgroup/dbe61/Kconfig ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/artecgroup/dbe61/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -9,7 +9,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR Modified: trunk/src/mainboard/digitallogic/msm800sev/Kconfig ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/digitallogic/msm800sev/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -10,7 +10,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -9,7 +9,6 @@ select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select PIRQ_ROUTE - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR Modified: trunk/src/mainboard/lippert/hurricane-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/hurricane-lx/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/lippert/hurricane-lx/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -10,7 +10,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/lippert/literunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/literunner-lx/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/lippert/literunner-lx/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -11,7 +11,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/lippert/roadrunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/lippert/roadrunner-lx/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -10,7 +10,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM # Standard chip is a 512 KB FWH. Replacing it with a 1 MB # SST 49LF008A is possible. select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/lippert/spacerunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/lippert/spacerunner-lx/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -11,7 +11,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/pcengines/alix1c/Kconfig ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/pcengines/alix1c/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -10,7 +10,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR Modified: trunk/src/mainboard/pcengines/alix2d/Kconfig ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/pcengines/alix2d/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -9,7 +9,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR Modified: trunk/src/mainboard/traverse/geos/Kconfig ============================================================================== --- trunk/src/mainboard/traverse/geos/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/traverse/geos/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -9,7 +9,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR Modified: trunk/src/mainboard/winent/pl6064/Kconfig ============================================================================== --- trunk/src/mainboard/winent/pl6064/Kconfig Mon Sep 27 23:15:56 2010 (r5870) +++ trunk/src/mainboard/winent/pl6064/Kconfig Mon Sep 27 23:18:26 2010 (r5871) @@ -10,7 +10,6 @@ select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
