Author: uwe Date: Fri Oct 1 09:27:51 2010 New Revision: 5890 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5890
Log: CAR simplifications, typos, readability improvements (trivial). - Use some more #defines instead of hard-coding values. - Merge multiple movl/orl or movl/andl lines into one where possible. - Add some TODOs in places which seem to have either an incorrect code or incorrect comment. - Fix typos: s/for/from/, s/BSC/BSP/, s/size/carsize/. Signed-off-by: Uwe Hermann <[email protected]> Acked-by: Uwe Hermann <[email protected]> Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/include/cpu/x86/mtrr.h Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Fri Oct 1 08:27:35 2010 (r5889) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Fri Oct 1 09:27:51 2010 (r5890) @@ -90,7 +90,7 @@ */ movl $0x1b, %ecx rdmsr - bt $8, %eax /* BSC */ + bt $8, %eax /* BSP */ jnc CAR_FAM10_out /* Enable RT tables on BSP. */ @@ -135,15 +135,14 @@ wrmsr #if CONFIG_MMCONF_SUPPORT - /* Set MMIO Config space BAR. */ + /* Set MMIO config space BAR. */ movl $MSR_MCFG_BASE, %ecx rdmsr - andl $(~(0xfff00000 | (0xf << 2))), %eax - orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000) | (8 << 2) | (1 << 0)), %eax + orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000), %eax + orl $((8 << 2) | (1 << 0)), %eax andl $(~(0x0000ffff)), %edx orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx - wrmsr #endif @@ -216,7 +215,7 @@ .endm /* - * size is the cache size in bytes we want to use for CAR. + * carsize is the cache size in bytes we want to use for CAR. * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset @@ -289,7 +288,7 @@ /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ + movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax wrmsr /* Enable the MTRRs and IORRs in SYSCFG. */ @@ -302,7 +301,7 @@ /* Enable cache. */ movl %cr0, %eax - andl $0x9fffffff, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 jmp_if_k8(fam10_end_part1) @@ -310,7 +309,7 @@ /* So we need to check if it is BSP. */ movl $0x1b, %ecx rdmsr - bt $8, %eax /* BSC */ + bt $8, %eax /* BSP */ jnc CAR_FAM10_ap fam10_end_part1: @@ -365,7 +364,7 @@ movl $0xc001001f, %ecx /* NB_CFG_MSR */ rdmsr movl %edi, %ecx /* CoreID bits */ - bt $(54-32), %edx + bt $(54 - 32), %edx jc roll_cfg rolb %cl, %bl roll_cfg: Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 08:27:35 2010 (r5889) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 09:27:51 2010 (r5890) @@ -110,7 +110,7 @@ /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ + movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax wrmsr /* Clear all MTRRs. */ @@ -169,7 +169,7 @@ .endm /* - * size is the cache size in bytes we want to use for CAR. + * carsize is the cache size in bytes we want to use for CAR. * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset @@ -221,8 +221,7 @@ */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax + movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx @@ -233,7 +232,7 @@ /* Enable cache. */ movl %cr0, %eax - andl $0x9fffffff, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -303,7 +302,7 @@ pushl %eax /* BIST */ call main - /* We don't need CAR for now on. */ + /* We don't need CAR from now on. */ /* Disable cache. */ movl %cr0, %eax @@ -332,7 +331,7 @@ /* Enable cache. */ movl %cr0, %eax - andl $0x9fffffff, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 /* Clear boot_complete flag. */ Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 08:27:35 2010 (r5889) +++ trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 09:27:51 2010 (r5890) @@ -45,7 +45,7 @@ /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ + movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax wrmsr /* Clear all MTRRs. */ @@ -100,8 +100,7 @@ */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax + movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx @@ -109,13 +108,16 @@ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr + /* Set the default memory type and enable fixed and variable MTRRs. */ + /* TODO: Or also enable fixed MTRRs? Bug in the code? */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000800, %eax /* Enable variable and fixed MTRRs. */ + movl $(MTRRdefTypeEn), %eax wrmsr + /* Enable cache. */ movl %cr0, %eax - andl $0x9fffffff, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -186,27 +188,24 @@ * want to go back. */ - /* We don't need CAR for now on. */ + /* We don't need CAR from now on. */ /* Disable cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 - /* - * Set the default memory type and disable fixed and enable - * variable MTRRs. - */ + /* Set the default memory type and enable variable MTRRs. */ + /* TODO: Or also enable fixed MTRRs? Bug in the code? */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000800, %eax /* Enable variable & disable fixed MTRRs. */ + movl $(MTRRdefTypeEn), %eax wrmsr /* Enable caching for first 1M using variable MTRR. */ movl $MTRRphysBase_MSR(0), %ecx xorl %edx, %edx - movl $(0 | 6), %eax - // movl $(0 | MTRR_TYPE_WRBACK), %eax + movl $(0 | MTRR_TYPE_WRBACK), %eax wrmsr /* @@ -223,8 +222,7 @@ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(0x80000 | 6), %eax - orl $(0 | 6), %eax + movl $(0x80000 | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx @@ -234,8 +232,7 @@ movl $MTRRphysBase_MSR(2), %ecx xorl %edx, %edx - movl $(0xc0000 | 6), %eax - orl $(0 | 6), %eax + movl $(0xc0000 | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(2), %ecx @@ -246,21 +243,17 @@ /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ movl $MTRRphysBase_MSR(3), %ecx xorl %edx, %edx - movl $REAL_XIP_ROM_BASE,%eax - orl $(0 | 6), %eax + movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(3), %ecx xorl %edx, %edx - movl $CONFIG_XIP_ROM_SIZE, %eax - decl %eax - notl %eax - orl $(0 | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr /* Enable cache. */ movl %cr0, %eax - andl $0x9fffffff, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 invd Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Fri Oct 1 08:27:35 2010 (r5889) +++ trunk/src/include/cpu/x86/mtrr.h Fri Oct 1 09:27:51 2010 (r5890) @@ -15,6 +15,9 @@ #define MTRRcap_MSR 0x0fe #define MTRRdefType_MSR 0x2ff +#define MTRRdefTypeEn (1 << 11) +#define MTRRdefTypeFixEn (1 << 10) + #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
