Hi,
attached patch moves CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into
Kconfig, renames it slightly, makes it visible only on relevant
northbridges, drops it entirely from via boards (as they seem to have
picked it up from AMD code without using it themselves), and make it
default to false for all boards.
Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.
Signed-off-by: Patrick Georgi <[email protected]>
Patrick
Index: src/Kconfig
===================================================================
--- src/Kconfig (Revision 5895)
+++ src/Kconfig (Arbeitskopie)
@@ -499,6 +499,16 @@
If unsure, say N.
+config HAVE_DEBUG_CAR
+ def_bool n
+
+config DEBUG_CAR
+ bool "Output verbose Cache-as-RAM debug messages"
+ default n
+ depends on HAVE_DEBUG_CAR
+ help
+ This option enables additional CAR related debug messages.
+
config DEBUG_PIRQ
bool "Check PIRQ table consistency"
default n
Index: src/mainboard/iwill/dk8_htx/romstage.c
===================================================================
--- src/mainboard/iwill/dk8_htx/romstage.c (Revision 5895)
+++ src/mainboard/iwill/dk8_htx/romstage.c (Arbeitskopie)
@@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/iwill/dk8s2/romstage.c
===================================================================
--- src/mainboard/iwill/dk8s2/romstage.c (Revision 5895)
+++ src/mainboard/iwill/dk8s2/romstage.c (Arbeitskopie)
@@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/iwill/dk8x/romstage.c
===================================================================
--- src/mainboard/iwill/dk8x/romstage.c (Revision 5895)
+++ src/mainboard/iwill/dk8x/romstage.c (Arbeitskopie)
@@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/supermicro/h8dmr/ap_romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr/ap_romstage.c (Revision 5895)
+++ src/mainboard/supermicro/h8dmr/ap_romstage.c (Arbeitskopie)
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/supermicro/h8dme/ap_romstage.c
===================================================================
--- src/mainboard/supermicro/h8dme/ap_romstage.c (Revision 5895)
+++ src/mainboard/supermicro/h8dme/ap_romstage.c (Arbeitskopie)
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/gigabyte/m57sli/ap_romstage.c
===================================================================
--- src/mainboard/gigabyte/m57sli/ap_romstage.c (Revision 5895)
+++ src/mainboard/gigabyte/m57sli/ap_romstage.c (Arbeitskopie)
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/gigabyte/ma78gm/romstage.c
===================================================================
--- src/mainboard/gigabyte/ma78gm/romstage.c (Revision 5895)
+++ src/mainboard/gigabyte/ma78gm/romstage.c (Arbeitskopie)
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
Index: src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c (Revision 5895)
+++ src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c (Arbeitskopie)
@@ -25,7 +25,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/gigabyte/ma785gmt/romstage.c
===================================================================
--- src/mainboard/gigabyte/ma785gmt/romstage.c (Revision 5895)
+++ src/mainboard/gigabyte/ma785gmt/romstage.c (Arbeitskopie)
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
Index: src/mainboard/amd/serengeti_cheetah/ap_romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/ap_romstage.c (Revision 5895)
+++ src/mainboard/amd/serengeti_cheetah/ap_romstage.c (Arbeitskopie)
@@ -2,7 +2,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/amd/serengeti_cheetah/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/romstage.c (Revision 5895)
+++ src/mainboard/amd/serengeti_cheetah/romstage.c (Arbeitskopie)
@@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/amd/mahogany_fam10/romstage.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/romstage.c (Revision 5895)
+++ src/mainboard/amd/mahogany_fam10/romstage.c (Arbeitskopie)
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
Index: src/mainboard/amd/tilapia_fam10/romstage.c
===================================================================
--- src/mainboard/amd/tilapia_fam10/romstage.c (Revision 5895)
+++ src/mainboard/amd/tilapia_fam10/romstage.c (Arbeitskopie)
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
Index: src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c (Revision 5895)
+++ src/mainboard/amd/serengeti_cheetah_fam10/romstage.c (Arbeitskopie)
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
Index: src/mainboard/iei/kino-780am2-fam10/romstage.c
===================================================================
--- src/mainboard/iei/kino-780am2-fam10/romstage.c (Revision 5895)
+++ src/mainboard/iei/kino-780am2-fam10/romstage.c (Arbeitskopie)
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
Index: src/mainboard/tyan/s2912/ap_romstage.c
===================================================================
--- src/mainboard/tyan/s2912/ap_romstage.c (Revision 5895)
+++ src/mainboard/tyan/s2912/ap_romstage.c (Arbeitskopie)
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/via/epia-m700/romstage.c
===================================================================
--- src/mainboard/via/epia-m700/romstage.c (Revision 5895)
+++ src/mainboard/via/epia-m700/romstage.c (Arbeitskopie)
@@ -23,7 +23,6 @@
*/
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define PAYLOAD_IS_SEABIOS 0
#include <stdint.h>
Index: src/mainboard/msi/ms9282/romstage.c
===================================================================
--- src/mainboard/msi/ms9282/romstage.c (Revision 5895)
+++ src/mainboard/msi/ms9282/romstage.c (Arbeitskopie)
@@ -23,7 +23,6 @@
*/
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/msi/ms9185/romstage.c
===================================================================
--- src/mainboard/msi/ms9185/romstage.c (Revision 5895)
+++ src/mainboard/msi/ms9185/romstage.c (Arbeitskopie)
@@ -24,7 +24,6 @@
*/
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/msi/ms7260/ap_romstage.c
===================================================================
--- src/mainboard/msi/ms7260/ap_romstage.c (Revision 5895)
+++ src/mainboard/msi/ms7260/ap_romstage.c (Arbeitskopie)
@@ -24,7 +24,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1 /* Used by RAM init. */
#define QRANK_DIMM_SUPPORT 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
Index: src/mainboard/msi/ms7260/romstage.c
===================================================================
--- src/mainboard/msi/ms7260/romstage.c (Revision 5895)
+++ src/mainboard/msi/ms7260/romstage.c (Arbeitskopie)
@@ -20,7 +20,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
// #define RAM_TIMING_DEBUG 1
// #define DQS_TRAIN_DEBUG 1
// #define RES_DEBUG 1
Index: src/mainboard/jetway/pa78vm5/romstage.c
===================================================================
--- src/mainboard/jetway/pa78vm5/romstage.c (Revision 5895)
+++ src/mainboard/jetway/pa78vm5/romstage.c (Arbeitskopie)
@@ -23,7 +23,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
Index: src/mainboard/nvidia/l1_2pvv/ap_romstage.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/ap_romstage.c (Revision 5895)
+++ src/mainboard/nvidia/l1_2pvv/ap_romstage.c (Arbeitskopie)
@@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1
Index: src/mainboard/asus/m4a785-m/romstage.c
===================================================================
--- src/mainboard/asus/m4a785-m/romstage.c (Revision 5895)
+++ src/mainboard/asus/m4a785-m/romstage.c (Arbeitskopie)
@@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
Index: src/mainboard/asus/a8v-e_se/romstage.c
===================================================================
--- src/mainboard/asus/a8v-e_se/romstage.c (Revision 5895)
+++ src/mainboard/asus/a8v-e_se/romstage.c (Arbeitskopie)
@@ -24,8 +24,6 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
unsigned int get_sbdn(unsigned bus);
/* Used by raminit. */
Index: src/mainboard/asus/m2v-mx_se/romstage.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/romstage.c (Revision 5895)
+++ src/mainboard/asus/m2v-mx_se/romstage.c (Arbeitskopie)
@@ -24,8 +24,6 @@
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
unsigned int get_sbdn(unsigned bus);
/* Used by raminit. */
Index: src/northbridge/via/vx800/examples/romstage.c
===================================================================
--- src/northbridge/via/vx800/examples/romstage.c (Revision 5895)
+++ src/northbridge/via/vx800/examples/romstage.c (Arbeitskopie)
@@ -21,7 +21,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#include <stdint.h>
#include <device/pci_def.h>
Index: src/northbridge/amd/amdk8/Kconfig
===================================================================
--- src/northbridge/amd/amdk8/Kconfig (Revision 5895)
+++ src/northbridge/amd/amdk8/Kconfig (Arbeitskopie)
@@ -21,6 +21,7 @@
bool
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
+ select HAVE_DEBUG_CAR
select HYPERTRANSPORT_PLUGIN_SUPPORT
config AGP_APERTURE_SIZE
Index: src/northbridge/amd/amdk8/debug.c
===================================================================
--- src/northbridge/amd/amdk8/debug.c (Revision 5895)
+++ src/northbridge/amd/amdk8/debug.c (Arbeitskopie)
@@ -3,13 +3,9 @@
*
*/
-#ifndef CACHE_AS_RAM_ADDRESS_DEBUG
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-#endif
-
static inline void print_debug_addr(const char *str, void *val)
{
-#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
+#if CONFIG_DEBUG_CAR
printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str,
val);
#endif
}
Index: src/northbridge/amd/amdfam10/Kconfig
===================================================================
--- src/northbridge/amd/amdfam10/Kconfig (Revision 5895)
+++ src/northbridge/amd/amdfam10/Kconfig (Arbeitskopie)
@@ -21,6 +21,7 @@
bool
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
+ select HAVE_DEBUG_CAR
select HYPERTRANSPORT_PLUGIN_SUPPORT
select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
select MMCONF_SUPPORT
Index: src/northbridge/amd/amdfam10/debug.c
===================================================================
--- src/northbridge/amd/amdfam10/debug.c (Revision 5895)
+++ src/northbridge/amd/amdfam10/debug.c (Arbeitskopie)
@@ -26,7 +26,7 @@
static inline void print_debug_addr(const char *str, void *val)
{
-#if defined(CACHE_AS_RAM_ADDRESS_DEBUG) && CACHE_AS_RAM_ADDRESS_DEBUG == 1
+#if CONFIG_DEBUG_CAR
printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str,
val);
#endif
}
--
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