Author: zbao Date: Fri Oct 8 05:35:12 2010 New Revision: 5922 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5922
Log: Trivial. Fix the typo. Signed-off-by: Zheng Bao <[email protected]> Acked-by: Zheng Bao <[email protected]> Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctsrc.c Fri Oct 8 01:42:17 2010 (r5921) +++ trunk/src/northbridge/amd/amdmct/mct/mctsrc.c Fri Oct 8 05:35:12 2010 (r5922) @@ -848,7 +848,7 @@ struct DCTStatStruc *pDCTstat) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is 1/2 Memclock Delay * Read Position is 1/2 Memclock Delay */ @@ -863,7 +863,7 @@ struct DCTStatStruc *pDCTstat, u8 Channel) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is no Delay * Read Position is 1/2 Memclock Delay */ Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Fri Oct 8 01:42:17 2010 (r5921) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Fri Oct 8 05:35:12 2010 (r5922) @@ -800,7 +800,7 @@ struct DCTStatStruc *pDCTstat) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is 1/2 Memclock Delay * Read Position is 1/2 Memclock Delay */ @@ -814,7 +814,7 @@ struct DCTStatStruc *pDCTstat, u8 Channel) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is no Delay * Read Position is 1/2 Memclock Delay */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
