Author: zbao Date: Sat Oct 9 04:31:10 2010 New Revision: 5927 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5927
Log: Trivial. Spell checking. Signed-off-by: Zheng Bao <[email protected]> Acked-by: Zheng Bao <[email protected]> Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h trunk/src/northbridge/amd/amdmct/mct/mct_d.h trunk/src/northbridge/amd/amdmct/mct/mctardk3.c trunk/src/northbridge/amd/amdmct/mct/mctardk4.c trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct.h Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mct.h Sat Oct 9 04:31:10 2010 (r5927) @@ -110,7 +110,7 @@ #define Mod64BitMux 4 /* func 2, offset A0h, bit 4 */ #define DisableJitter 1 /* func 2, offset A0h, bit 1 */ #define DramEnabled 9 /* func 2, offset A0h, bit 9 */ -#define SyncOnUcEccEn 2 /* fun 3, offset 44h, bit 2 */ +#define SyncOnUcEccEn 2 /* func 3, offset 44h, bit 2 */ /*============================================================================= Jedec DDR II @@ -349,7 +349,7 @@ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFail; /* Bitmap showing the chanel informaiton about failed Chip Selects*/ + u16 ChannelTrainFail; /* Bitmap showing the channel information about failed Chip Selects*/ /* 0 in any bit field indicates Channel 0*/ /* 1 in any bit field indicates Channel 1*/ }; @@ -509,7 +509,7 @@ #endif -// global function +/* global function */ u32 NodePresent(u32 Node); u32 Get_NB32n(struct DCTStatStruc *pDCTstat, u32 addrx); u32 Get_NB32(u32 addr); /* NOTE: extend addr to 32 bit for bus > 0 */ Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.h Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.h Sat Oct 9 04:31:10 2010 (r5927) @@ -236,7 +236,7 @@ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ /*----------------------------- - Jdec DDR II related equates + Jedec DDR II related equates -----------------------------*/ #define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ #define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ @@ -436,7 +436,7 @@ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFai; /* Bitmap showing the chanel informaiton about failed Chip Selects + u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects 0 in any bit field indicates Channel 0 1 in any bit field indicates Channel 1 */ u16 CSUsrTestFail; /* Chip selects excluded by user */ @@ -471,7 +471,7 @@ u8 MaxDCTs; /* Max number of DCTs in system*/ // NOTE: removed u8 DCT. Use ->dev_ for pci R/W; /*DCT pointer*/ u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/ - u8 DRPresent; /* Family 10 present flag, 0 = n0t Fam10, 1 = Fam10*/ + u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/ u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk3.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctardk3.c Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mctardk3.c Sat Oct 9 04:31:10 2010 (r5927) @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 021100xFF301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ @@ -128,7 +128,7 @@ * #1, BYTE, Speed (DCTStatstruc.Speed) (Secondary Key) * #2, BYTE, number of Address bus loads on the Channel. (Tershery Key) * These must be listed in ascending order. - * FFh (0xFE) has special meanying of 'any', and must be listed first for each speed grade. + * FFh (0xFE) has special meaning of 'any', and must be listed first for each speed grade. * #3, DWORD, Address Timing Control Register Value * #4, DWORD, Output Driver Compensation Control Register Value * #5, BYTE, Number of DIMMs (Primary Key) Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk4.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Sat Oct 9 04:31:10 2010 (r5927) @@ -59,7 +59,7 @@ * #1, BYTE, Speed (DCTStatstruc.Speed) * #2, BYTE, number of Address bus loads on the Channel. * These must be listed in ascending order. - * FFh (-1) has special meanying of 'any', and must be listed first for + * FFh (-1) has special meaning of 'any', and must be listed first for * each speed grade. * #3, DWORD, Address Timing Control Register Value * #4, DWORD, Output Driver Compensation Control Register Value Modified: trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Sat Oct 9 04:31:10 2010 (r5927) @@ -134,7 +134,7 @@ /* Bug#15880: Determine validity of reset settings for DDR PHY timing * regi.. - * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR2 training. + * Solution: At least, set WrDqs fine delay to be 0 for DDR2 training. */ u32 dev; Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Sat Oct 9 04:31:10 2010 (r5927) @@ -263,7 +263,7 @@ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ /*----------------------------- - Jdec DDR II related equates + Jedec DDR II related equates -----------------------------*/ #define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ #define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ @@ -464,7 +464,7 @@ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFai; /* Bitmap showing the chanel informaiton about failed Chip Selects + u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects 0 in any bit field indicates Channel 0 1 in any bit field indicates Channel 1 */ u16 DIMMTfaw; /* Minimax Tfaw*16 (ns) of DIMMs */ @@ -513,7 +513,7 @@ u8 MaxDCTs; /* Max number of DCTs in system*/ /* NOTE: removed u8 DCT. Use ->dev_ for pci R/W; */ /*DCT pointer*/ u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/ - u8 DRPresent; /* Family 10 present flag, 0 = n0t Fam10, 1 = Fam10*/ + u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/ u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
