On Mon, Oct 11, 2010 at 9:41 PM, Idwer Vollering <[email protected]> wrote: > 2010/10/12 Keith Hui <[email protected]> >> >> Guys, > > Hi Keith, >> >> I could no longer boot my P3B-F with my Tualeron and r5938. Dies with >> "unknown CPU". I believe it will happen with any Slot 1 440BX boards >> that supports model_6bx CPUs. > > Can you confirm that this changeset caused the regression: > http://tracker.coreboot.org/trac/coreboot/changeset/5909 ? Not that one directly. This regression was caused by the entire cpu/intel/model_6bx branch not being pulled in for cpu/intel/slot_1 so the Tualatin cpuids are missing from the whitelist. So it must be one of the patches when we tried to clean up the Makefiles and forgot that model_6bx is a possibility for slot 1 boards and needs to be included..
>> >> I need to make the change below to make it work. abuild tested. Boot >> tested on P2B-LS and P3B-F. > > > In which directory does this changed file reside, src/cpu/intel/slot_1/ or > src/cpu/intel/model_6bx/ ? > src/cpu/intel/slot_1 Thanks for the catch. Updated below. >> >> After we split the rest of the P6 family from model_6xx, a similar >> change will need to be made here. >> Signed-off-by: Keith Hui <[email protected]> >> >> 8<------------------------- Index: Makefile.inc =================================================================== --- src/cpu/intel/slot_1/Makefile.inc (revision 5938) +++ src/cpu/intel/slot_1/Makefile.inc (working copy) @@ -20,6 +20,7 @@ ramstage-y += slot_1.c subdirs-y += ../model_6xx +subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
