]From: [email protected] [mailto:[email protected]] On Behalf Of Arne Georg ]Gleditsch ] ]"Scott Duplichan" <[email protected]> writes: ]> I find with my RS780/SB700 board (ECS A780GM-M3), the initial ]> family 10h AP launch is not reliable. I often see a hang when ]> when all the cores are running in parallel. The parallel execution ]> is apparent if serial logging is enabled, because the characters ]> logged by each core are interleaved. I noticed the AP cores do a ]> few cf8/cfc pci config writes. Could simultaneous access to this ]> shared index/data pair be responsible for the hang? Concerns about ]> such conflicts is why the AMD agesa code does not run cores on the ]> same die in parallel. ] ]This is actually the main reason I fixed MMCONFIG for AMD boards, since ]that avoids the cf8/cfc race. I would suggest enabling that, but you ]might have to change the default address range. I believe there's a BAR ]that's assigned a temporary address by the RS780 code that would clash.
Hello Arne, Thanks. Enabling MMIO config space access makes a huge improvement. I already had everything esle ready. All I had to do was enable CONFIG_MMCONF_SUPPORT_DEFAULT. Now the problem appears to be solved. Great work on this feature. Thanks, Scott ]-- ] Arne. -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
