On Mon, Oct 18, 2010 at 6:48 AM, Arne Georg Gleditsch <[email protected]> wrote: > Rudolf Marek <[email protected]> writes: >> Please can you help here? Also I tried to have a look how the non-posted >> support >> could be added but it looks like it must be done somewhat inside the resource >> allocator. Please can you help with that too? Basically we would need to put >> some MMIO resources which have non-posted attribute set in resource (this >> must >> be done) to be allocated somewhat together so only one MMIO resource would be >> needed (and we need to modify the northbridge.c of K8 to set the non-posted >> bit) > > On a similar note: I'm looking at a southbridge that has its own notion > of what constitutes TOP_OF_DRAM. Apparently, the IOMMU aperture needs > to be below this boundary, or DMA transactions towards the aperture are > terminated with master abort. From the CPU's side, though, the IOMMU > aperture should be above TOP_OF_MEM, in order to avoid wasting the DRAM > behind it, no? So, as well as being able to allocate posted and > non-posted memory resources in separate hunks: in this instance it would > be good to be able to allocate the GART aperture in a third hunk that > was placed below the other two, so that the SB TOM register could be > programmed to include it when needed. > > Is this feasible, or should I approach this from a different angle?
It sounds like overkill to include this as a special case for the resource allocator. At first glance, the code would seem to be very simple for that register. Is this a one-time, one-resource problem? Are there other hunks that need to be allocated together with it? Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
