Author: jakllsch Date: Tue Oct 19 17:17:18 2010 New Revision: 5974 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5974
Log: Use the correct (W83627THF, not W83627HF) superio code in MS-7135 romstage. This is consistent with the device tree and the chip actually on the board. Trivial. Signed-off-by: Jonathan Kollasch <[email protected]> Acked-by: Jonathan Kollasch <[email protected]> Modified: trunk/src/mainboard/msi/ms7135/romstage.c Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 19 16:02:10 2010 (r5973) +++ trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 19 17:17:18 2010 (r5974) @@ -22,7 +22,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, W83627THF_SP1) /* Used by raminit. */ #define QRANK_DIMM_SUPPORT 1 @@ -41,7 +41,7 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "superio/winbond/w83627thf/w83627thf_early_serial.c" #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> @@ -135,7 +135,7 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
