Sorry for the span. I attribute it to some kind of quarks mode. Mark Beihoffer Dragonfly Networks [email protected] [email protected] (612)508-5128
On Fri, Oct 22, 2010 at 9:14 AM, <[email protected]> wrote: > Send coreboot mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.coreboot.org/mailman/listinfo/coreboot > or, via email, send a message with subject or body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of coreboot digest..." > > > Today's Topics: > > 1. Mark Beihoffer has invited you to open a Google mail account > (Mark Beihoffer) > 2. Resource allocator problem? (was: Re: Want to participate in > ASUS M2V(K8T890/VT8237A) testing) (Tobias Diedrich) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Fri, 22 Oct 2010 07:58:10 -0500 > From: Mark Beihoffer <[email protected]> > To: [email protected] > Subject: [coreboot] Mark Beihoffer has invited you to open a Google > mail account > Message-ID: > <[email protected]> > Content-Type: text/plain; charset="utf-8" > > I've been using Gmail and thought you might like to try it out. Here's an > invitation to create an account. > > > You're Invited to Gmail! > > Mark Beihoffer has invited you to open a Gmail account. > > Gmail is Google's free email service, built on the idea that email can be > intuitive, efficient, and fun. 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Learn > more<http://mail.google.com/mail/help/intl/en/about.html>or get > started< > http://mail.google.com/mail/a-273fae0330-b83fc009ac-kCWmf2yFIP99-wBkiFmp7ts6KwU > > > ! > Sign up< > http://mail.google.com/mail/a-273fae0330-b83fc009ac-kCWmf2yFIP99-wBkiFmp7ts6KwU > > > > Google Inc. | 1600 Ampitheatre Parkway | Mountain View, California 94043 > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://www.coreboot.org/pipermail/coreboot/attachments/20101022/4b62769e/attachment-0001.html > > > > ------------------------------ > > Message: 2 > Date: Fri, 22 Oct 2010 16:14:01 +0200 > From: Tobias Diedrich > <[email protected]<ranma%[email protected]> > > > To: [email protected] > Subject: [coreboot] Resource allocator problem? (was: Re: Want to > participate in ASUS M2V(K8T890/VT8237A) testing) > Message-ID: <[email protected]> > Content-Type: text/plain; charset="us-ascii" > > Scott Duplichan wrote: > > ]PCI: 00:01.0 bridge ctrl <- 0017 > > ]PCI: 00:01.0 cmd <- 04 > > ]PCI: 00:02.0 bridge ctrl <- 0003 > > ]PCI: 00:02.0 cmd <- 00 > > ]PCI: 00:03.0 bridge ctrl <- 0003 > > ]PCI: 00:03.0 cmd <- 07 > > ][hang] > > ] > > ]00:03.0 is one of the onboard pcie devices. > > ] > > ]-- > > ]Tobias PGP: > http://8ef7ddba.uguu.de > > > > The write of 07 enables memory bars, I/O bars, and bus master > > for that device. You could try to dump the config space for that > > device to see if memory and I/O bars are reasonable. Knowing > > MTRRs and TOM would let you confirm the memory bars point to UC-IO. > > Ok, it's a problem with the resource allocator. > It's allocating io 0x000-0xfff to this bridge, and the existing > 'avoid legacy ports' checks don't seem to catch this. > > |Done setting resources. > |Show resources in subtree (Root Device)...After assigning values. > |[...] > | PCI: 00:03.0 child on link 0 PCI: 03:00.0 > | PCI: 00:03.0 resource base 0 size 1000 align 12 gran 12 limit ffff > flags 60080102 index 1c > | PCI: 00:03.0 resource base fecbffff size 0 align 20 gran 20 limit > fecbffff flags 60081202 in > | PCI: 00:03.0 resource base f0000000 size 100000 align 20 gran 20 limit > fecbffff flags 600802 > | PCI: 03:00.0 > | PCI: 03:00.0 resource base 10 size 8 align 3 gran 3 limit ffff flags > 60000100 index 10 > | PCI: 03:00.0 resource base 20 size 4 align 2 gran 2 limit ffff flags > 60000100 index 14 > | PCI: 03:00.0 resource base 18 size 8 align 3 gran 3 limit ffff flags > 60000100 index 18 > | PCI: 03:00.0 resource base 24 size 4 align 2 gran 2 limit ffff flags > 60000100 index 1c > | PCI: 03:00.0 resource base 0 size 10 align 4 gran 4 limit ffff flags > 60000100 index 20 > | PCI: 03:00.0 resource base f0000000 size 400 align 10 gran 10 limit > fecbffff flags 60000200 > | PCI: 00:03.1 child on link 0 PCI: 04:00.0 > | PCI: 00:03.1 resource base 1000 size 1000 align 12 gran 12 limit ffff > flags 60080102 index 1 > > The devices/device.c has two checks to defend legacy ports in > compute_resources and allocate_resources: > > | if (resource->flags & IORESOURCE_IO) { > | /* Don't allow potential aliases over the legacy > PCI > | * expansion card addresses. The legacy PCI decodes > | * only 10 bits, uses 0x100 - 0x3ff. Therefore, > only > | * 0x00 - 0xff can be used out of each 0x400 block > of > | * I/O space. > | */ > | if ((base & 0x300) != 0) { > | base = (base & ~0x3ff) + 0x400; > | } > | /* Don't allow allocations in the VGA I/O range. > | * PCI has special cases for that. > | */ > | else if ((base >= 0x3b0) && (base <= 0x3df)) { > | base = 0x3e0; > | } > | } > > This doesn't prevent the bridge from getting allocated 0x0000-0x0fff. > > I added > | /* exclude 0x0000 - 0x0400 legacy range */ > | if (base <= 0x400) { > | base = 0x400; > | } > > and now it's booting and handing off to seabios (but video card init > doesn't seem to work). > > |Done setting resources. > |Show resources in subtree (Root Device)...After assigning values. > |[...] > | PCI: 00:03.0 child on link 0 PCI: 03:00.0 > | PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ffff > flags 60080102 index 1 > | PCI: 00:03.0 resource base fecbffff size 0 align 20 gran 20 limit > fecbffff flags 60081202 in > | PCI: 00:03.0 resource base f0000000 size 100000 align 20 gran 20 limit > fecbffff flags 600802 > | PCI: 03:00.0 > | PCI: 03:00.0 resource base 1010 size 8 align 3 gran 3 limit ffff > flags 60000100 index 10 > | PCI: 03:00.0 resource base 1020 size 4 align 2 gran 2 limit ffff > flags 60000100 index 14 > | PCI: 03:00.0 resource base 1018 size 8 align 3 gran 3 limit ffff > flags 60000100 index 18 > | PCI: 03:00.0 resource base 1024 size 4 align 2 gran 2 limit ffff > flags 60000100 index 1c > | PCI: 03:00.0 resource base 1000 size 10 align 4 gran 4 limit ffff > flags 60000100 index 20 > | PCI: 03:00.0 resource base f0000000 size 400 align 10 gran 10 limit > fecbffff flags 60000200 > | PCI: 00:03.1 child on link 0 PCI: 04:00.0 > | PCI: 00:03.1 resource base 2000 size 1000 align 12 gran 12 limit ffff > flags 60080102 index 1 > | PCI: 00:03.1 resource base fecbffff size 0 align 20 gran 20 limit > fecbffff flags 60081202 in > | PCI: 00:03.1 resource base f0100000 size 100000 align 20 gran 20 limit > fecbffff flags 600802 > |[...] > |Start bios (version pre-0.6.2-20101020_194120-nukunuku) > |Found mainboard ASUS M2V > |Found CBFS header at 0xfffffc6e > |Ram Size=0xdfff0000 (0x0000000100000000 high) > |Relocating init from 0x000e9330 to 0xdffd6880 (size 38496) > |CPU Mhz=1001 > |Found 1 cpu(s) max supported 1 cpu(s) > |Copying MPTABLE from 0xdfff0400/dfff0410 to 0x000fda50 > |SMBIOS ptr=0x000fda30 table=0xdffefed0 > |Scan for VGA option rom > |EHCI init on dev 00:10.4 (regs=0xf0300010) > |Found 0 lpt ports > |Found 2 serial ports > |ATA controller 0 at 1f0/3f4/0 (irq 14 dev 79) > |ATA controller 1 at 170/374/0 (irq 15 dev 79) > |ATA controller 2 at 1010/1020/0 (irq 0 dev 300) > |ATA controller 3 at 1018/1024/0 (irq 0 dev 300) > |ata1-1: Pioneer DVD-ROM ATAPIModel DVD-106S 0122 ATAPI-5 DVD/CD > |PS2 keyboard initialized > |All threads complete. > |Scan for option roms > |Press F12 for boot menu. > > -- > Tobias PGP: > http://8ef7ddba.uguu.de > -------------- next part -------------- > A non-text attachment was scrubbed... > Name: coreboot_try14.log.gz > Type: application/octet-stream > Size: 12081 bytes > Desc: not available > URL: < > http://www.coreboot.org/pipermail/coreboot/attachments/20101022/19fa48b8/attachment.obj > > > > ------------------------------ > > _______________________________________________ > coreboot mailing list > [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot > > End of coreboot Digest, Vol 68, Issue 118 > ***************************************** >
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