The patch (attached) was tested by a user on IRC who had the F71889FG. I
wrote it using documentation from Fintek's website available here:
http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf
This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for
chip ID bytes 1 & 2. However, I have not been able to find documentation to
verify that the two chips are identical from superiotool's perspective.
The F71889 seems popular on current generation platforms with AMD chipsets,
in case there are folks looking to try it on a presently unsupported
board...
Signed-off-by: David Hendricks <[email protected]>
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
Index: fintek.c
===================================================================
--- fintek.c (revision 5953)
+++ fintek.c (working copy)
@@ -122,6 +122,50 @@
{0x30,0xf0,0xf1,0xf4,0xf5,EOT},
{0x00,0x00,0x01,0x06,0x1c,EOT}},
{EOT}}},
+ {0x2307, "F71889FG", {
+ /* We assume reserved bits are read as 0. */
+ {NOLDN, NULL,
+ {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,
+ 0x2b,0x2c,0x2d,EOT},
+ {0x05,0x41,0x19,0x34,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x08,0x08,EOT}},
+ {0x0, "Floppy",
+ {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
+ {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
+ {0x1, "COM1",
+ {0x30,0x60,0x61,0x70,0xf0,EOT},
+ {0x01,0x03,0xf8,0x04,0x00,EOT}},
+ {0x2, "COM2",
+ {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+ {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}},
+ {0x3, "Parallel port",
+ {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
+ {0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
+ {0x4, "Hardware monitor",
+ {0x30,0x60,0x61,0x70,EOT},
+ {0x01,0x02,0x95,0x00,EOT}},
+ {0x5, "Keyboard",
+ {0x30,0x60,0x61,0x70,0x72,0xf0,EOT},
+ {0x01,0x00,0x60,0x00,0x00,0x83,EOT}},
+ {0x6, "GPIO",
+ {0x70,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1,0xd2,0xd3,0xc0,
+ 0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xf0,0xf1,0xf2,
+ 0xf3,EOT},
+ {0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,
+ 0x0f,NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0xff,NANA,
+ 0x00,EOT}},
+ {0x7, "VID",
+ {0x30,0x60,0x61,EOT},
+ {0x00,0x00,0x00,EOT}},
+ {0x7, "SPI",
+ {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,
+ 0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+ {0x10,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,EOT}},
+ {0xa, "PME, ACPI",
+ {0x30,0xf0,0xf1,0xf4,0xf5,EOT},
+ {0x00,0x00,0x01,0x06,0x1c,EOT}},
+ {EOT}}},
{0x0604, "F71805F/FG", {
/* We assume reserved bits are read as 0. */
{NOLDN, NULL,
--
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