Hi Dustin,
> I have never seen that kind of output when using Truxton. All I can
> suggest is to make sure your serial settings are correct and double
> check any modifications you may have made to the coreboot source.
I will check my serial settings and send the new output.
> Note though, trunk does not support non-ECC RAM. The raminit_ep80579.c
> code will refuse to boot if it detects non-ECC RAM.
I saw that and attached is a small patch we did to bypass the non-ecc ram check
in raminit_ep80579.c
Do you know how we can modify this test to use coreboot w/ non-ecc RAM ?
My best regards,
Xavier.
> Dustin
>
> On 05/11/2010 3:00 AM, Xavier Carcelle wrote:
>
>
> Hi there,
>
>
> I am currently testing coreboot for the Intel EP80579 w/ the Truxton
> platform w/ DDR2 (not ECC) on the DIMM0 slot of the platform. I am
> having the following bootlog but don't understand what is the output
> meaning ?
>
>
> Thanks,
>
>
> Xavier.
>
>
>
> "coreboot-4.0-r5689
>
> coreboot-4.0-r5689 50AI 00
> 01 51AI 00
> 01 52AI 00
> 01 53AI 0080 08 08 0e 0a 00 40 00 05 3d 50 00 82 08 00 00 AI 100c 08
> 38 01 02 00 03 3d 50 50 60 3c 1e 3c 2d 01 AI 2025 37 10 220
> 01 55AI 00
> 01 56AI 00
> 01 57AI 00ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff AI 10ff ff
> ff ff ff ff ff ff ff ff ff ff ff ff ff ff AI 20ff ff ff ff
> 00
>
>
> 00
> MHz DDR
> Sc cd` - 25c cd` - 0000000000000201` - c cd` - DR
> ffffffffDRB = 00000000
> TOM = 0000
> TOLM = 0000
> cl = 00
> trc = 7e
> trfc = 00
> tras = 00
> trtp = 40
> twtr = 00
> drt0 = ffffffea
> drt1 = fc700000
> magic = 009a62b1
> mrs = 69020000
> 0000T @Q000000000000000000000000000000000010T
> @Q000000000000000000000000000000000020T
> @Q000000000000000000000000000000000030T @0
> ``c` CS01
> q00000010DDR
> R
> 00T @QR
> 01T @Q0000T @Q001000000000000000000000000000000010T
> @Q000000000000000000000000000000000020T
> @Q0000000000000000000000000000000000
> 0000T @Q001000000000000000000000000000000010T
> @Q000000000000000000000000000000000020T
> @Q000000000000000000000000000000000030T @S
> 00:00.0000: 86 80 20 50 06 00 10 00 01 00 00 06 00 00 80 00 10: 00 00
> 00 00 00 00 00 90 00 00 00 00 00 00 00 00 20: 00 00 00 00"
>
>
> --
> coreboot mailing list: [email protected]
> http://www.coreboot.org/mailman/listinfo/coreboot
Index: i3100/raminit_ep80579.c
===================================================================
--- i3100/.svn/text-base/raminit_ep80579.c.svn-base 2010-09-09 22:34:04.000000000 +0200
+++ i3100/raminit_ep80579.c 2010-09-09 22:41:12.000000000 +0200
@@ -26,6 +26,8 @@
#define BAR 0x90000000
+static unsigned ecc_capable;
+
static void sdram_set_registers(const struct mem_controller *ctrl)
{
static const u32 register_values[] = {
@@ -423,8 +425,8 @@
continue;
if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40)
die("ERROR: Only 64-bit DIMMs supported\n");
- if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02))
- die("ERROR: Only ECC DIMMs supported\n");
+ if (spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02)
+ ecc_capable = 1;
if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08)
die("ERROR: Only x8 DIMMs supported\n");
@@ -436,7 +438,10 @@
print_debug_hex8(cycle);
print_debug("\n");
- drc |= (1 << 20); /* enable ECC */
+ if (ecc_capable)
+ drc |= (1 << 20); /* enable ECC */
+ else
+ drc &= ~(1 << 20); /* disable ECC */
drc |= (3 << 30); /* enable CKE on each DIMM */
drc |= (1 << 4); /* enable CKE globally */
@@ -756,7 +761,11 @@
print_debug("clear memory CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
+ if (ecc_capable)
+ data32 = ((cs+1)<<20);
+ else
+ data32 = ~((cs+1)<<20);
+ write32(BAR+MBCSR, 0xa00000f0 | (data32 | (0<<16));
data32 = read32(BAR+MBCSR);
while (data32 & 0x80000000)
data32 = read32(BAR+MBCSR);
--
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