Scott Duplichan wrote: > MTRR related improvements for AMD family 10h and family 0Fh systems > > -- When building for UMA, reduce the limit for DRAM below 4GB > from E0000000 to C0000000. This is needed to accomodate the > UMA frame buffer. > -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En > and Tom2ForceMemTypeWB) are not set consistently across cores. > -- Enable TOM2 only if DRAM is present above 4GB. > -- Use AMD Tom2ForceMemTypeWB feature to avoid the need for > variable MTRR ranges above 4GB. > -- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing > this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for > DRAM above 4GB. AMD systems use this option to conserve MTRRs. > -- Northbridge.c change to deduct UMA memory from DRAM size reported > by ram_resource. This corrects a problem where mtrr.c generates an > unexpected variable MTRR range. > -- Correct problem causing build failure when CONFIG_GFXUMA=1 and > CONFIG_VAR_MTRR_HOLE=0. > -- Reserve the UMA DRAM range for AMD K8 as is already done for AMD > family 10h. > Tested with mahogany on ECS A780G-GM with 2GB and 4GB. > Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB. > > Signed-off-by: Scott Duplichan <[email protected]>
Acked-by: Peter Stuge <[email protected]> -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
