Author: jakllsch Date: Sun Nov 21 23:55:46 2010 New Revision: 6109 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6109
Log: Move CK804_PCI_E_X and CK804B_PCI_E_X defines (which have been 4 by default on all boards) into Kconfig. Signed-off-by: Jonathan Kollasch <[email protected]> Acked-by: Uwe Hermann <[email protected]> Modified: trunk/src/southbridge/nvidia/ck804/Kconfig trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Modified: trunk/src/southbridge/nvidia/ck804/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Kconfig Sun Nov 21 23:47:22 2010 (r6108) +++ trunk/src/southbridge/nvidia/ck804/Kconfig Sun Nov 21 23:55:46 2010 (r6109) @@ -5,30 +5,42 @@ select IOAPIC select TINY_BOOTBLOCK +if SOUTHBRIDGE_NVIDIA_CK804 + config BOOTBLOCK_SOUTHBRIDGE_INIT string - default "southbridge/nvidia/ck804/bootblock.c" if SOUTHBRIDGE_NVIDIA_CK804 + default "southbridge/nvidia/ck804/bootblock.c" config ID_SECTION_OFFSET hex - default 0x80 if SOUTHBRIDGE_NVIDIA_CK804 + default 0x80 config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804 + default 0xfef00000 config EHCI_DEBUG_OFFSET hex - default 0x98 if SOUTHBRIDGE_NVIDIA_CK804 + default 0x98 config CK804_USE_NIC bool - default n if SOUTHBRIDGE_NVIDIA_CK804 + default n config CK804_USE_ACI bool - default n if SOUTHBRIDGE_NVIDIA_CK804 + default n + +config CK804_PCI_E_X + int + default 4 + +config CK804B_PCI_E_X + int + default 4 config CK804_NUM int - default 1 if SOUTHBRIDGE_NVIDIA_CK804 + default 1 + +endif Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Sun Nov 21 23:47:22 2010 (r6108) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Sun Nov 21 23:55:46 2010 (r6109) @@ -56,16 +56,15 @@ #define SYSCTRL_REG_POS 0x64 /* + * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. + * Apparently some sort of lane configuration. + * * 16 1 1 2 :0 * 8 8 2 2 :1 * 8 8 4 :2 * 8 4 4 4 :3 * 16 4 :4 -*/ - -#ifndef CK804_PCI_E_X -#define CK804_PCI_E_X 4 -#endif + */ #if CONFIG_CK804_NUM > 1 #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000) @@ -73,9 +72,6 @@ #ifndef CK804B_BUSN #define CK804B_BUSN 0x80 #endif -#ifndef CK804B_PCI_E_X -#define CK804B_PCI_E_X 4 -#endif #endif #define CK804_CHIP_REV 3 @@ -258,9 +254,9 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), #if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), #endif RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Sun Nov 21 23:47:22 2010 (r6108) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Sun Nov 21 23:55:46 2010 (r6109) @@ -54,20 +54,15 @@ #define SYSCTRL_REG_POS 0x64 /* + * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. + * Apparently some sort of lane configuration. + * * 16 1 1 2 :0 * 8 8 2 2 :1 * 8 8 4 :2 * 8 4 4 4 :3 * 16 4 :4 -*/ - -#ifndef CK804_PCI_E_X -#define CK804_PCI_E_X 4 -#endif - -#ifndef CK804B_PCI_E_X -#define CK804B_PCI_E_X 4 -#endif + */ #define CK804_CHIP_REV 3 @@ -199,7 +194,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), //SYSCTRL RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), @@ -275,7 +270,7 @@ /* This line doesn't exist in the non-CAR version. */ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), #if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
